Semiconductor device and memory circuit having an OS transistor and a capacitor

Patent metadata

Field	Value
Publication number	US-10388380-B2
Application number	US-201715823662-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	May 22, 2014
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90 . Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor including an oxide semiconductor in a channel formation region;
second to fourth transistors;
a capacitor; and
first to fifth wirings,
wherein:
the first wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor,
the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor and one of electrodes of the capacitor,
a gate of the first transistor is electrically connected to the second wiring,
the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor,
a gate of the second transistor is electrically connected to the third wiring,
the other of the source and the drain of the third transistor is electrically connected to the other of electrodes of the capacitor and the fourth wiring, and
a gate of the fourth transistor is electrically connected to the fifth wiring;
wherein the second wiring is configured to provide a first voltage and the third wiring is configured to provide a second voltage different from the first voltage.

2. The semiconductor device according to claim 1 , wherein the semiconductor device is a first memory circuit.

3. The semiconductor device according to claim 2 , wherein the first memory circuit overlaps with at least a part of an arithmetic circuit.

4. The semiconductor device according to claim 1 , wherein each of the first wiring and the fourth wiring is electrically connected to a driver circuit which has functions of writing data.

5. The semiconductor device according to claim 4 , wherein the second wiring is electrically connected to a driver circuit which has a function of selecting a second memory circuit.

6. The semiconductor device according to claim 1 , wherein the second wiring is electrically connected to a driver circuit which has a function of selecting a second memory circuit.

7. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the fourth transistor is electrically connected to an arithmetic circuit.

8. A semiconductor device comprising:
a first memory circuit;
a second memory circuit, the second memory circuit comprising:
a first transistor including an oxide semiconductor in a channel formation region;
second to fourth transistors; and
a capacitor, and
first to fifth wirings,

wherein:
the first wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor,
the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor and one of electrodes of the capacitor,
a gate of the first transistor is electrically connected to the second wiring,
the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor,
a gate of the second transistor is electrically connected to the third wiring,
the other of the source and the drain of the third transistor is electrically connected to the other of electrodes of the capacitor and the fourth wiring,
a gate of the fourth transistor is electrically connected to the fifth wiring,
the first memory circuit is configured to store data acquired from an outside, and
the second memory circuit is configured to store reference data;
wherein the second wiring is configured to provide a first voltage and the third wiring is configured to provide a second voltage different from the first voltage.

9. The semiconductor device according to claim 8 , wherein each of the first wiring and the fourth wiring is electrically connected to a driver circuit which has functions of writing data.

10. The semiconductor device according to claim 9 , wherein the second wiring is electrically connected to a driver circuit which has a function of selecting the first memory circuit.

11. The semiconductor device according to claim 8 , wherein the second wiring is electrically connected to a driver circuit which has a function of selecting the first memory circuit.

12. The semiconductor device according to claim 8 , wherein the other of the source and the drain of the fourth transistor is electrically connected to an arithmetic circuit.

13. The semiconductor device according to claim 8 , wherein the second memory circuit overlaps with at least a part of an arithmetic circuit.

14. The semiconductor device according to claim 8 further comprising an arithmetic circuit, wherein the arithmetic circuit is configured to compare the data and the reference data.

Assignees

• Semiconductor Energy Lab

Inventors

• Tamura Hikaru

Classifications

• G11C7/1078 Primary

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C11/40

  using transistors · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title