Electronic Device

Patent metadata

Field	Value
Publication number	US-2016343452-A1
Application number	US-201615158860-A
Country	US
Kind code	A1
Filing date	May 19, 2016
Priority date	May 21, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

First claim

What is claimed is:

1 . An electronic device comprising:
a first circuit comprising a first transistor, a second transistor, and a capacitor; a second circuit comprising a third transistor; and first to sixth wirings, wherein: a gate of the first transistor is electrically connected to the first wiring, a first terminal of the first transistor is electrically connected to the second wiring, a second terminal of the first transistor is electrically connected to a gate of the second transistor, a first terminal of the capacitor is electrically connected to the third wiring, a second terminal of the capacitor is electrically connected to the gate of the second transistor, a first terminal of the second transistor is electrically connected to the fourth wiring, a gate of the third transistor is electrically connected to the third wiring, a first terminal of the third transistor is electrically connected to the fifth wiring, a second terminal of the second transistor is electrically connected to the sixth wiring, and a second terminal of the third transistor is electrically connected to the sixth wiring.

2 . The electronic device according to claim 1 ,
wherein the first circuit is part of an artificial neural array.

3 . The electronic device according to claim 1 , configured to calculate a modification amount of a gate potential of the second transistor by using at least one of a current flowing through the fourth wiring and a current flowing through the fifth wiring.

4 . The electronic device according to claim 1 , wherein a channel formation region of the first transistor comprises an oxide semiconductor.

5 . The electronic device according to claim 3 , wherein the first transistor comprises a backgate.

6 . An electronic device comprising:
first circuits arranged in rows and columns, each first circuit comprising a first transistor, a second transistor, and a capacitor; second circuits arranged in a column, each second circuit comprising a third transistor; first wirings, second wirings, third wirings, fourth wirings, a fifth wiring, and sixth wirings; a row decoder; a column decoder; an input circuit; and an output circuit, wherein: for each row of the first circuits, gates of the first transistors are electrically connected to the row decoder via one of the first wirings, for each column of the first circuits, first terminals of the first transistors are electrically connected to the column decoder via one of the second wirings, for each first circuit, a second terminal of the first transistor is electrically connected to a gate of the second transistor, for each row of the first circuits, a first terminal of the capacitor is electrically connected to the input circuit via one of the third wirings, for each first circuit, a second terminal of the capacitor is electrically connected to the gate of the second transistor, for each column of the first circuits, a first terminal of the second transistor is electrically connected to the output circuit via one of the fourth wirings, for each second circuit, a gate of the third transistor is electrically connected to one of the third wirings, and for each second circuit, a first terminal of the third transistor is electrically connected to the output circuit via the fifth wiring.

7 . The electronic device according to claim 6 ,
wherein the first circuits form an artificial neural array.

8 . The electronic device according to claim 6 , configured to calculate a modification amount of a gate potential of the second transistors by using current flowing through the fourth wirings or current flowing through the fifth wiring.

9 . The electronic device according to claim 6 , wherein channel formation regions of the first transistors comprise an oxide semiconductor.

10 . The electronic device according to claim 9 , wherein the first transistors each comprise a backgate.

11 . An electronic device comprising:
first circuits arranged in rows and columns, each first circuit comprising a first transistor, a second transistor, and a capacitor; second circuits arranged in a column, each second circuit comprising a third transistor; first wirings, second wirings, third wirings, fourth wirings, a fifth wiring, and sixth wirings; a row decoder; a column decoder; an input circuit; an output circuit; an analog signal processing circuit functionally connected to the output circuit; and a memory functionally connected to the analog signal processing circuit and the first circuits, wherein: for each row of the first circuits, gates of the first transistors are electrically connected to the row decoder via one of the first wirings, for each column of the first circuits, first terminals of the first transistors are electrically connected to the column decoder via one of the second wirings, for each first circuit, a second terminal of the first transistor is electrically connected to a gate of the second transistor, for each row of the first circuits, a first terminal of the capacitor is electrically connected to the input circuit via one of the third wirings, for each first circuit, a second terminal of the capacitor is electrically connected to the gate of the second transistor, for each column of the first circuits, a first terminal of the second transistor is electrically connected to the output circuit via one of the fourth wirings, for each second circuit, a gate of the third transistor is electrically connected to one of the third wirings, and for each second circuit, a first terminal of the third transistor is electrically connected to the output circuit via the fifth wiring.

12 . The electronic device according to claim 11 ,
wherein the first circuits form an artificial neural array.

13 . The electronic device according to claim 1 ,
wherein: the first circuits form an artificial neural array, the analog signal processing circuit is configured to calculate a modification amount of weight based on data output from the output circuit, and wherein the memory is configured to store the modification amount of weight.

14 . The electronic device according to claim 13 , configured to use the modification amount of weight stored in the memory for calculating a new modification amount of weight in a learning operation.

15 . The electronic device according to claim 11 , configured to calculate a modification amount of a gate potential of the second transistors by using current flowing through the fourth wirings or current flowing through the fifth wiring.

16 . The electronic device according to claim 11 , wherein channel formation regions of the first transistors comprise an oxide semiconductor.

17 . The electronic device according to claim 11 , wherein the first transistors each comprise a backgate.

Assignees

• Semiconductor Energy Lab

Inventors

• Ikeda Takayuki
• Kurokawa Yoshiyuki

Classifications

• G11C27/024 Primary

  using a capacitive memory element (G11C27/04 takes precedence) · CPC title

• G06N3/065

  Analogue means · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title