Fin field effect transistor having airgap and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12165925-B2
Application number	US-202318354670-A
Country	US
Kind code	B2
Filing date	Jul 19, 2023
Priority date	Jul 31, 2018
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

First claim

What is claimed is:

1. A fin field effect transistor (FinFET), comprising:
a substrate;
a plurality of fins, standing on the substrate and extending along a first direction, the plurality of fins being separated by insulators;
a plurality of gates, disposed over the plurality of fins and extending along a second direction, the first direction being different from the second direction, and the plurality of gates covering portions of the plurality of fins; and
a plurality of source/drain elements, covering portions of the plurality of fins exposed by the plurality of gates, wherein bottoms of the plurality of source/drain elements are above bottoms of the insulators,
wherein an air gap is disposed on the insulators with a bottom of the air gap being lower than top surfaces of the insulators.

2. The FinFET of claim 1 , wherein the air gap is further disposed at positions between two adjacent gates of the plurality of gates along the first direction and positions between two adjacent fins of the plurality of fins along the second direction.

3. The FinFET of claim 1 , further comprising:
a cap layer, over the substrate and extending onto the plurality of fins, the plurality of source/drain elements and the plurality of gates, the cap layer further extending into the air gap.

4. The FinFET of claim 1 ,
wherein the insulators are trench isolation structures, and the insulators are disposed inside trenches of the trench isolation structures, wherein the air gap is overlapped with the insulators in a stacking direction of the plurality of fins and the substrate.

5. The FinFET of claim 4 , further comprising:
a cap layer, over the substrate and extending onto the insulators, the plurality of source/drain elements and the plurality of gates.

6. The FinFET of claim 1 , wherein the air gap is further disposed in the FinFET at positions between the plurality of gates and the substrate in a stacking direction of the plurality of fins and the substrate.

7. The FinFET of claim 1 , further comprising:
a plurality of gate contacts, disposed on and electrically coupled to the plurality of gates; and
a plurality of source/drain contacts, disposed on and electrically coupled to the plurality of source/drain elements,
wherein the air gap is further disposed in the FinFET at positions between two adjacent source/drain contacts of the plurality of source/drain contacts and positions between two adjacent source/drain elements of the plurality of source/drain elements.

8. A fin field effect transistor (FinFET), comprising:
a plurality of fins, separated from one another by a plurality of trenches;
a plurality of gates, disposed over the plurality of fins, the plurality of gates covering first portions of the plurality of fins and portions of the plurality of trenches, wherein an air gap is laterally disposed in the FinFET at positions between two adjacent gates of the plurality of gates;
a plurality of source/drain elements, covering second portions of the plurality of fins next to the first portions and exposed by the plurality of gates; and
a cap film, disposed over the plurality of gates and further extending into the air gap and the plurality of trenches.

9. The FinFET of claim 8 , further comprising:
a plurality of insulators, lining the plurality of trenches, wherein an outer surface of each of the plurality of insulators is exposed to the air gap.

10. The FinFET of claim 9 , wherein the plurality of fins are separated from the cap layer by the plurality of insulators.

11. The FinFET of claim 8 , wherein the air gap is further disposed in the FinFET at positions inside the plurality of trenches.

12. The FinFET of claim 8 , wherein the air gap is further disposed in the FinFET at positions between two adjacent fins of the plurality of fins.

13. The FinFET of claim 8 , wherein the air gap is further disposed in the FinFET at positions between two adjacent source/drain elements of the plurality of source/drain elements.

14. The FinFET of claim 8 , further comprising:
a plurality of gate contacts, disposed on and electrically coupled to the plurality of gates; and
a plurality of source/drain contacts, disposed on and electrically coupled to the plurality of source/drain elements,
wherein the air gap is further disposed in the FinFET at positions between two adjacent source/drain contacts of the plurality of source/drain contacts and positions between two adjacent source/drain elements of the plurality of source/drain elements.

15. A fin field effect transistor (FinFET), comprising:
a plurality of gates, disposed over a plurality of semiconductor fins;
a plurality of source/drain elements, covering portions of the plurality of semiconductor fins exposed by the plurality of gates; and
a cap layer, wherein an air gap is disposed in the FinFET at positions laterally between two adjacent semiconductor fins of the plurality of semiconductor fins, and the cap layer extends onto the plurality of semiconductor fins, the plurality of source/drain elements and the plurality of gates.

16. The FinFET of claim 15 , wherein the plurality of semiconductor fins are separated from one another by a plurality of trenches, and the air gap is further disposed in the FinFET at positions inside the plurality of trenches.

17. The FinFET of claim 16 , further comprising:
a plurality of insulators, disposed inside the plurality of trenches and covering sidewalls of the plurality of semiconductor fins, wherein the air gap is overlapped with the plurality of insulators in a lateral direction substantially perpendicular to a stacking direction of the plurality of semiconductor fins and the plurality of source/drain elements.

18. The FinFET of claim 15 , wherein the air gap is further disposed in the FinFET at positions between the plurality of gates and the plurality of insulators in a stacking direction of the plurality of semiconductor fins and the plurality of source/drain elements.

19. The FinFET of claim 15 , further comprising:
a plurality of gate contacts, disposed on and electrically coupled to the plurality of gates; and
a plurality of source/drain contacts, disposed on and electrically coupled to the plurality of source/drain elements,
wherein the air gap is further disposed in the FinFET at positions between two adjacent source/drain contacts of the plurality of source/drain contacts and positions between two adjacent source/drain elements of the plurality of source/drain elements.

20. The FinFET of claim 15 , wherein the air gap is further disposed in the FinFET at positions underneath the plurality of gates in a stacking direction of the plurality of semiconductor fins and the plurality of source/drain elements.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeong Sai-Hooi
• LEE Kai-Hsuan
• Lin Yu-Ming
• Chui Chi-On

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title