Method of forming a sensor device having moisture sensitive dielectric layer with integrally formed projections

Patent metadata

Field	Value
Publication number	US-12159848-B2
Application number	US-202318501319-A
Country	US
Kind code	B2
Filing date	Nov 3, 2023
Priority date	Feb 11, 2021
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. More particularly, the present disclosure relates to a method of forming a sensor device and a bond pad in the same dielectric region. The present disclosure also relates to the semiconductor devices formed by the method disclosed herein.

First claim

What is claimed is:

1. A semiconductor device comprising:
a dielectric region;
a plurality of electrodes in the dielectric region;
a passivation layer on upper surfaces of each electrode in the plurality of electrodes;
a barrier layer on the passivation layer;
a moisture sensitive dielectric layer on the barrier layer, wherein the barrier layer is vertically between the plurality of electrodes and the moisture sensitive dielectric layer; and
a plurality of projections integrally formed with the moisture sensitive dielectric layer, the projections extending into the dielectric region, wherein each projection is between two electrodes in the plurality of electrodes.

2. The semiconductor device of claim 1 , wherein each projection is separated from each electrode by the material of the dielectric region.

3. The semiconductor device of claim 1 , wherein the projections extend through the dielectric region to contact an etch stop layer disposed below the dielectric region.

4. The semiconductor device of claim 1 , wherein each projection in the plurality of projections has a lower surface, each electrode in the plurality of electrodes has a lower surface, and the lower surface of each projection is substantially coplanar with the lower surface of each electrode.

5. The semiconductor device of claim 1 , wherein each projection in the plurality of projections has a lower surface, each electrode in the plurality of electrode has a lower surface, and the lower surface of each projection is at a level above the lower surface of each electrode.

6. The semiconductor device of claim 1 , further comprising a first etch stop layer below the dielectric region and a second etch stop layer within the dielectric region, wherein the projections extend through the dielectric region and the second etch stop layer to contact the first etch stop layer.

7. The semiconductor device of claim 1 , further comprising an etch stop layer within the dielectric region, wherein each projection in the plurality of projections has a lower surface and the lower surface of each projection is above and spaced apart from the etch stop layer.

8. The semiconductor device of claim 1 , further comprising an etch stop layer within the dielectric region, wherein the projections extend through the dielectric region and terminate on contact with the etch stop layer.

9. The semiconductor device of claim 1 , wherein the barrier layer and the passivation layer cover only the upper surfaces of each electrode in the plurality of electrodes.

10. The semiconductor device of claim 1 , wherein the moisture sensitive dielectric layer includes a hygroscopic organic polymer.

11. A method of forming a semiconductor device comprising:
forming a plurality of electrodes in a dielectric region;
forming a passivation layer on each electrode in the plurality of electrodes;
forming a barrier layer on the passivation layer;
forming a plurality of trenches that extend through the barrier layer and into the dielectric region; and
forming a moisture sensitive dielectric layer on the barrier layer, the barrier layer is formed vertically between the plurality of electrodes and the moisture sensitive dielectric layer, wherein the forming of the moisture sensitive dielectric layer also fills the trenches to form a plurality of projections, each projection being formed between two electrodes in the plurality of electrodes.

12. The method of claim 11 , wherein the forming of the trenches includes simultaneously etching the dielectric region and the barrier layer.

13. The method of claim 12 , wherein the dielectric region is exposed to the same etch process as the barrier layer.

14. The method of claim 12 , further comprising:
forming a plurality of recesses in the dielectric region by patterning the passivation layer and the dielectric region; and
forming the barrier layer to fill the recesses.

15. The method of claim 14 , wherein each recess is formed between two electrodes in the plurality of electrodes.

16. The method of claim 12 , wherein the forming of the trenches includes etching the dielectric region until bottom surfaces of the trenches contact a first etch stop layer formed below the dielectric region.

17. The method of claim 16 , wherein the etching of the dielectric region includes etching through a second etch stop layer formed within the dielectric region.

18. The method of claim 11 , wherein each projection is formed to be separated from each electrode by a material of the dielectric region.

19. The method of claim 11 , wherein the plurality of electrodes is formed in the dielectric region using a dual damascene process.

20. The method of claim 11 , wherein the moisture sensitive dielectric layer and the plurality of projections are formed to include a dielectric material that has a dielectric constant that changes as a function of relative humidity.

Assignees

• Globalfoundries Sg Pte Ltd
• Globalfoundries Singapore Ptd Ltd

Inventors

• KHOR Ee Jan
• Tan Juan Boon
• Chockalingam Ramasamy

Classifications

• H10W72/981

  Auxiliary members, e.g. spacers · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title