Integrated circuit with sensors and manufacturing method

Patent metadata

Field	Value
Publication number	US-9606079-B2
Application number	US-201313924218-A
Country	US
Kind code	B2
Filing date	Jun 21, 2013
Priority date	Jun 21, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Disclosed is an integrated circuit comprising a substrate ( 10 ) carrying plurality of circuit elements ( 20 ); a plurality of sensing electrodes ( 34 ) over said substrate, each sensing electrode being electrically connected to at least one of said circuit elements; and a plurality of wells ( 50 ) for receiving a sample, each sensing electrode defining the bottom of one of said wells, wherein each sensing electrode comprises at least one portion ( 34 ′) extending upwardly into said well. A method of manufacturing such an IC is also disclosed.

First claim

The invention claimed is:

1. An integrated circuit comprising:
a substrate carrying plurality of circuit elements;
a plurality of sensing electrodes over said substrate, at least one sensing electrode being electrically connected to at least one of said circuit elements;
a plurality of wells for receiving a sample, the at least one sensing electrode defining a bottom of at least one of said wells, wherein the at least one sensing electrode comprises a portion extending upwardly into said well and said portion laterally separated from side walls of the well;
wherein the portion extending upwardly has a first lateral side and a second lateral side; and
wherein the portion extending upwardly is configured to permit the sample to enter between the first lateral side of the portion and a first one of the side walls, and to permit the sample to enter between the second lateral side of the portion and a second one of the side walls.

2. The integrated circuit of claim 1 ,
wherein each sensing electrode comprises an ion-sensitive layer.

3. The integrated circuit of claim 1 , further comprising:
a metallization stack over said substrate for providing interconnections to at least some of said circuit elements,
the metallization stack comprising a plurality of patterned metal layers spatially separated from each other by respective electrically insulating layers,
at least some of said electrically insulating layers comprising conductive portions for electrically interconnecting portions of adjacent metal layers,
wherein at least one of the patterned metallization layers comprises the plurality of sensing electrodes,
wherein some of said conductive portions define said upwardly extending sensing electrode portions; and
wherein the plurality of wells extend into said metallization stack, each well terminating at one of said sensing electrodes.

4. The integrated circuit of claim 3 , further comprising
a patterned passivation layer over said metallization stack,
said patterned passivation layer comprises at least one aperture extending through said passivation layer providing access to and/or forming at least a part of one of said wells.

5. The integrated circuit of claim 4 ,
wherein the patterned passivation layer comprises a plurality of said apertures, each aperture forming part of a respective well.

6. The integrated circuit of claim 3 ,
wherein the metallization stack further comprises a first patterned metal layer and a second patterned metal layer over the first patterned metal layer,
said first patterned metal layer comprising the plurality of sensing electrodes and the second patterned metal layer comprising a plurality of further apertures,
each well extending towards one of said sensing electrodes from one of said further apertures.

7. The integrated circuit of claim 6 ,
wherein the second patterned metal layer is conductively coupled to a bias voltage source.

8. The integrated circuit of claim 3 ,
wherein the metallization stack further comprises a passivation layer formed in between adjacent metal layers.

9. The integrated circuit of claim 1 ,
wherein each well has tapered sidewalls and/or a rectangular cross-section.

10. The integrated circuit of claim 1 ,
wherein at least some of said wells contain a bead, each of said beads comprising a nucleic acid chemically bound to said bead.

11. The integrated circuit of claim 1 ,
wherein the portion extending upwardly into said well is shaped as a pillar.

12. A method of manufacturing an integrated circuit, the method comprising:
providing a substrate carrying a plurality of circuit elements;
providing at least one sensing electrode over said substrate, the sensing electrode being electrically connected to at least one of said circuit elements;
forming a further layer over the sensing electrode;
opening said further layer to define a well for receiving a sample, the well terminating at the sensing electrode;
extending said sensing electrode by forming a conductive portion that extends upwardly from the electrode surface into said well, said conductive portion laterally separated from side walls of the well;
wherein the conductive portion has a first lateral side and a second lateral side; and
wherein the conductive portion is configured to permit the sample to enter between the first lateral side of the conductive portion and a first one of the side walls, and to permit the sample to enter between the second lateral side of the conductive portion and a second one of the side walls.

13. The method of claim 12 , further comprising lining the well with an ion-sensitive dielectric layer following the formation of said conductive portion.

14. The method of claim 12 ,
further comprising
providing a metallization stack over said substrate for providing interconnections to at least some of said circuit elements,

the metallization stack comprising
a plurality of patterned metal layers spatially separated from each other by respective electrically insulating layers,
at least some of said electrically insulating layers comprising conductive portions for electrically interconnecting portions of adjacent metal layers,
wherein at least one of the patterned metallization layers comprises the sensing electrode,
some of said conductive portions defining said upwardly extending electrode portion;

wherein the further layer comprises at least the upper electrically insulating layer of said metallization stack.

15. The method of claim 14 , further comprising
forming a passivation layer over the metallization stack and
planarizing the passivation layer prior to said patterning step,
wherein said opening step comprises forming a plurality of apertures extending through said passivation layer and terminating on the electrode,
each of said apertures forming at least a part of the well.

16. The method of claim 14 ,
wherein the metallization stack further comprises a first patterned metal layer and a second patterned metal layer over the first patterned metal layer,
said first patterned metal layer comprising the electrode and the second patterned metal layer comprising a plurality of further apertures,
wherein said opening step further comprises forming the well by selectively removing part of the further layer over said electrodes through said at least one of the further apertures.

Assignees

• Nxp Bv

Inventors

• Merz Matthias

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• B01L2300/0819

  Microarrays; Biochips · CPC title

• G01N27/4148

  Integrated circuits therefor, e.g. fabricated by CMOS processing · CPC title

• B01L2300/0893

  having a very large number of wells, microfabricated wells · CPC title

• B01L2200/12

  Specific details about manufacturing devices · CPC title