Integrated circuit with sensor and method of manufacturing such an integrated circuit

Patent metadata

Field	Value
Publication number	US-9941222-B2
Application number	US-201615069898-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Feb 22, 2011
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Disclosed is an integrated circuit comprising a substrate carrying a plurality of circuit elements; a metallization stack interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion; a passivation stack covering the metallization stack; and a sensor including a sensing material on the passivation stack, said sensor being coupled to the first metal portion by a via extending through the passivation stack. A method of manufacturing such an IC is also disclosed.

First claim

The invention claimed is:

1. An integrated circuit comprising:
a substrate carrying a plurality of circuit elements;
a metallization stack interconnecting the circuit elements, the metallization stack including a patterned upper metallization layer having a first metal portion;
a passivation stack covering the metallization stack, the passivation stack including a moisture-impenetrable layer and being configured and arranged to mitigate moisture penetration to the metallization stack and ensure operation of the circuit elements; and
a sensor including a sensing material deposited on top of the passivation stack, the sensing material being coupled to the first metal portion by a via extending through the passivation stack,
wherein the sensor including the sensing material is deposited above the moisture-impenetrable layer, and
wherein the passivation stack and the via provide a contiguous moisture barrier over the first metal portion, the contiguous moisture barrier preventing moisture from contacting the first metal portion upon exposure of the sensor to moisture.

2. The integrated circuit of claim 1 , wherein the sensing material is deposited over the via.

3. The integrated circuit of claim 1 , wherein the passivation stack includes a Ta 2 O 5 layer, the sensing material being formed on the Ta 2 O 5 layer.

4. The integrated circuit of claim 3 , wherein the sensing material is formed on top of the Ta 2 O 5 layer.

5. A method of manufacturing an integrated circuit, comprising:
providing a substrate carrying a plurality of circuit elements;
forming a metallization stack interconnecting the circuit elements, the metallization stack including a patterned upper metallization layer having a first metal portion;
forming a passivation stack covering the metallization stack, the passivation stack including a moisture-impenetrable layer and being configured and arranged to mitigate moisture penetration to the metallization stack and ensure operation of the circuit elements;
forming a trench in the passivation stack to expose the first metal portion;
forming a via in the trench; and
forming a sensor including a sensing material by depositing the sensing material on top of the passivation stack, the sensing material being coupled to the first metal portion,
wherein the sensor including the sensing material is deposited above the moisture-impenetrable layer, and
wherein the passivation stack and the via are formed such that they provide a contiguous moisture barrier over the first metal portion, the contiguous moisture barrier preventing moisture from contacting the first metal portion upon exposure of the sensor to moisture.

6. The method according to claim 5 , wherein the sensing material is deposited over the via to couple the sensing material to the first metal portion.

7. The method according to claim 5 , wherein the passivation stack includes a Ta 2 O 5 layer, the sensing material being formed on the Ta 2 O 5 layer.

8. The method according to claim 7 , wherein the sensing material is formed on top of the Ta 2 O 5 layer.

Assignees

• Ams Int Ag

Inventors

• Daamen Roel
• Wolters Robertus Adrianus Maria
• Rongen Rene Theodora Hubertus
• Ponomarev Youri Victorovitch

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title