Semiconductor device and a method of operating the same

Patent metadata

Field	Value
Publication number	US-12156477-B2
Application number	US-202117314320-A
Country	US
Kind code	B2
Filing date	May 7, 2021
Priority date	Oct 16, 2020
Publication date	Nov 26, 2024
Grant date	Nov 26, 2024

Abstract

A semiconductor device includes a conductive pattern extending in a first direction, a magnetic tunnel junction pattern on the conductive pattern, and a capacitor on the magnetic tunnel junction pattern. The magnetic tunnel junction pattern is between the conductive pattern and the capacitor, and the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
a conductive pattern extending in a first direction, the conductive pattern having a first end portion and a second end portion opposite to each other in the first direction;
a magnetic tunnel junction pattern on the conductive pattern;
a capacitor on the magnetic tunnel junction pattern;
an upper conductive line connected to the first end portion of the conductive pattern; and
a contact plug connected to the second end portion of the conductive pattern, wherein
the magnetic tunnel junction pattern is between the conductive pattern and the capacitor,
the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern, and
the contact plug is offset from the magnetic tunnel junction pattern in the first direction, such that the contact plug is adjacent to the second end portion of the conductive pattern, and the upper conductive line is offset from the magnetic tunnel junction pattern in a direction opposite to the contact plug in the first direction, such that the upper conductive line is adjacent to a sidewall of the first end portion of the conductive pattern.

2. The semiconductor device of claim 1 , wherein the capacitor comprises: a bottom electrode;
a top electrode; and
a dielectric layer between the bottom electrode and the top electrode,
wherein the magnetic tunnel junction pattern connects to the bottom electrode of the capacitor.

3. The semiconductor device of claim 2 , further comprising:
a conductive pad between the magnetic tunnel junction pattern and the bottom electrode.

4. The semiconductor device of claim 1 , wherein
the upper conductive line is at one side of the conductive pattern and extending in a second direction that intersects the first direction.

5. The semiconductor device of claim 4 , further comprising:
a lower conductive line apart from the magnetic tunnel junction pattern with the conductive pattern between the lower conductive line and the magnetic tunnel junction pattern,
wherein the contact plug is between the conductive pattern and the lower conductive line.

6. The semiconductor device of claim 1 , wherein the magnetic tunnel junction pattern comprises:
a free magnetic pattern;
a reference magnetic pattern; and
a tunnel barrier pattern between the free and reference magnetic patterns,
wherein the free magnetic pattern is between the tunnel barrier pattern and the conductive pattern.

7. The semiconductor device of claim 6 , wherein magnetization directions of the free magnetic pattern and the reference magnetic pattern are at least one of substantially perpendicular to an interface between the free magnetic pattern and the conductive pattern or substantially parallel to the interface between the free magnetic pattern and the conductive pattern.

8. The semiconductor device of claim 1 , wherein the conductive pattern includes at least one of a heavy metal, a material doped with a heavy metal, or a topological insulator.

9. A semiconductor device comprising:
a capacitor on a substrate;
a magnetic tunnel junction pattern between the substrate and the capacitor and connected to the capacitor; and
a conductive pattern between the substrate and the magnetic tunnel junction pattern,
wherein the capacitor comprises,
a bottom electrode connected to the magnetic tunnel junction pattern,
a top electrode covering top and side surfaces of the bottom electrode in a direction perpendicular to an upper surface of the substrate, and
a dielectric layer between the top and side surfaces of the bottom electrode and the top electrode,
wherein the conductive pattern has a bar shape extending in a first direction that is parallel to a top surface of the substrate.

10. The semiconductor device of claim 9 , further comprising:
an upper conductive line at one side of the conductive pattern,
wherein the conductive pattern has a first sidewall and a second sidewall opposite to the first sidewall in the first direction, and
the upper conductive line connects to the first sidewall of the conductive pattern.

11. The semiconductor device of claim 10 , wherein the upper conductive line extends in a second direction which is parallel to the top surface of the substrate and which intersects the first direction.

12. The semiconductor device of claim 10 , further comprising:
a lower conductive line between the substrate and the conductive pattern and extending in the first direction; and
a contact plug connecting the conductive pattern to the lower conductive line,
wherein the contact plug is close to the second sidewall of the conductive pattern.

13. The semiconductor device of claim 12 , wherein the contact plug is offset from the magnetic tunnel junction pattern in the first direction, and the upper conductive line is offset from the magnetic tunnel junction pattern in a direction opposite to the first direction.

14. The semiconductor device of claim 9 , wherein the magnetic tunnel junction pattern comprises:
a free magnetic pattern;
a reference magnetic pattern; and
a tunnel barrier pattern between the free and reference magnetic patterns,
wherein one of the free magnetic pattern and the reference magnetic pattern is between the tunnel barrier pattern and the conductive pattern, and
the other of the free magnetic pattern and the reference magnetic pattern is between the bottom electrode and the tunnel barrier pattern.

15. The semiconductor device of claim 9 , wherein the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern by a current that is parallel to an interface between the magnetic tunnel junction pattern and the conductive pattern.

16. The semiconductor device of claim 9 , wherein the conductive pattern includes at least one of a heavy metal, a material doped with a heavy metal, or a topological insulator.

17. The semiconductor device of claim 9 , further comprising:
a conductive pad between the magnetic tunnel junction pattern and the bottom electrode.

18. A semiconductor device comprising:
a lower conductive line on a substrate and extending in a first direction that is parallel to a top surface of the substrate;
a plurality of contact plugs on the lower conductive line and spaced apart from each other in the first direction;
a plurality of conductive patterns on the plurality of contact plugs, respectively, and spaced apart from each other in the first direction;
a plurality of magnetic tunnel junction patterns on the plurality of conductive patterns, respectively; and
a capacitor on the magnetic tunnel junction patterns,
wherein the capacitor includes a plurality of bottom electrodes apart from each other in the first direction, and
the magnetic tunnel junction patterns connect to the bottom electrodes, respectively.

19. The semiconductor device of claim 18 , wherein each of the conductive patterns has a bar shape extending in the first direction.

20. The semiconductor device of claim 19 , further comprising:
a plurality of upper conductive lines on the lower conductive line and intersecting the lower conductive line,
wherein the upper conductive lines are apart from each other in the first direction and extend in a second direction which is parallel to the top surface of the substrate and intersects the first direction, and
the upper conductive lines connect to the conductive patterns, respectively.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jiho

Classifications

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10N50/85

  Materials of the active region · CPC title

• H10N50/80 Primary

  Constructional details · CPC title

• H10B61/20

  comprising components having three or more electrodes, e.g. transistors · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title