Integrated capacitor based power distribution

Patent metadata

Field	Value
Publication number	US-9305629-B2
Application number	US-201313976053-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein.

First claim

What is claimed is:

1. An apparatus comprising:
a supply voltage plane that includes an array of supply voltage lines;
a ground plane that includes an array of ground lines;
an array of capacitors formed from the arrays of supply voltage lines and ground lines;
a first capacitor, formed at a first intersection between a first supply voltage line, included in the array of supply voltage lines, and a first ground line, included in the array of ground lines; wherein the capacitor comprises a first plate that includes a portion of the first supply voltage line, a second plate that includes a portion of the first ground line, and a first dielectric formed between the first and second plates;
a device, to electrically couple to the capacitor, comprising at least one of a tunnel field-effect transistor, spin transfer torque (STT) memory, and a spin logic device; and
a switching element coupled to the capacitor and included within a switching mode power supply;
wherein (a) the array of capacitors, which includes the first capacitor, the device, and the switching element are all formed on a single monolithic substrate; and (b) the switching element discharges the capacitor to drive current between the first and second plates and then to the device.

2. The apparatus of claim 1 comprising:
a second capacitor, formed at a second intersection between a second supply voltage line, included in the array of supply voltage lines, and a second ground line, included in the array of ground lines; wherein the second capacitor comprises an additional first plate that includes a portion of the second supply voltage line, an additional second plate that includes a portion of the second ground line, and a second dielectric formed between the additional first and second plates;
wherein the power supply charges the first and second capacitors in series with one another during a charging mode and discharges the first and second capacitors in parallel with one another during a discharge mode.

3. The apparatus of claim 1 , wherein the array of capacitors are metal-insulator-metal (MiM) capacitors.

4. The apparatus of claim 1 , wherein:
the switching element includes first, second, and third switching devices;
the power supply charges the first capacitor during a first clock phase and discharges the first capacitor during a second clock phase that is opposite the first clock phase; and
the first switching device is active during the first clock phase and the second and third switching devices are active during the second clock phase.

5. The apparatus of claim 1 , wherein the power supply discharges the first capacitor orthogonally to the supply voltage plane to drive current between the first and second plates and then to the device.

6. The apparatus of claim 5 , wherein the power supply is a step down converter that steps supply voltage down from more than 1 V to less than 15 mV and supplies current greater than 90 A with a current density greater than 380 A/cm 2 .

7. The apparatus of claim 1 comprising an interconnect coupling the device to one of the first and second plates, wherein an axis orthogonal to the second plate intersects the first and second plates and the device.

8. The apparatus of claim 7 wherein (a) the device is a spin logic inverter comprising a magnetic layer portion directly contacting a metal layer portion, and (b) the axis intersects the magnetic and metal layer portions.

9. The apparatus of claim 1 wherein the first dielectric includes at least one of Hafnium Oxide, Ruthenium Oxide, Molybdenum Oxide, and LiMn 2 O 4 activated carbon.

10. The apparatus of claim 1 wherein the entire power supply is included on the substrate and is to couple to a battery located off the substrate.

Assignees

• Intel Corp

Inventors

• Manipatruni Sasikanth
• Nikonov Dmitri E
• Young Ian A

Classifications

• G11C11/1697 Primary

  Power supply circuits · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title