Integrated circuit devices including separate memory cells on separate regions of individual substrate

Patent metadata

Field	Value
Publication number	US-10468103-B2
Application number	US-201715826031-A
Country	US
Kind code	B2
Filing date	Nov 29, 2017
Priority date	Dec 1, 2016
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

First claim

What is claimed is:

1. An integrated circuit (IC) device, comprising:
an individual substrate configured to include a single chip; and
a plurality of memory cells on the substrate, the plurality of memory cells spaced apart from each other on the substrate, the plurality of memory cells having different structures,
wherein the plurality of memory cells includes a first memory cell and a second memory cell,
wherein the substrate includes
at least one first active region and at least one second active region spaced apart from each other, and
an isolation layer between the at least one first active region and the at least one second active region,

wherein the first memory cell is on the at least one first active region,
wherein the second memory cell is on the at least one second active region,
wherein the first memory cell includes a capacitor and a first transistor, and the second memory cell includes a variable resistance structure and a second transistor, and
wherein the first transistor includes a first source/drain region having a first doping concentration, the second transistor includes a second source/drain region having a second doping concentration, and the second doping concentration is greater than the first doping concentration.

2. The IC device of claim 1 , wherein the plurality of memory cells includes a DRAM memory cell and an MRAM memory cell.

3. The IC device of claim 1 , wherein,
the capacitor is spaced apart from the substrate by a first distance,
the variable resistance structure spaced apart from the substrate by a second distance, and
the second distance is different from the first distance.

4. The IC device of claim 3 , wherein the first distance is less than the second distance.

5. The IC device of claim 1 , wherein,
the capacitor has an uppermost surface, the uppermost surface spaced apart from the substrate by a first distance,
the variable resistance structure is spaced apart from the substrate by a second distance, and
the second distance is greater than the first distance.

6. The IC device of claim 1 , wherein,
the capacitor has an uppermost surface, the uppermost surface spaced apart from the substrate by a first distance,
the variable resistance structure is spaced apart from the substrate by a second distance, and
the second distance is less than the first distance.

Assignees

• Kim Sung Woo
• Lee Jae Kyu
• Suh Ki Seok
• Hong Hyeong Sun
• Hwang Yoo Sang
• Koh Gwan Hyeob
• Samsung Electronics Co Ltd

Inventors

• Kim Sung-Woo
• Lee Jae-Kyu
• Suh Ki-Seok
• Hong Hyeong-Sun
• Hwang Yoo-Sang
• Koh Gwan-Hyeob

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C14/0036 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C14/0045

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title