Hybrid memory and MTJ based MRAM bit-cell and array

Patent metadata

Field	Value
Publication number	US-10170185-B2
Application number	US-201315036761-A
Country	US
Kind code	B2
Filing date	Dec 24, 2013
Priority date	Dec 24, 2013
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.

First claim

We claim:

1. An apparatus comprising:
a capacitor having a first terminal and a second terminal;
a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to a bit line (BL), and a drain/source terminal coupled to the first terminal of the capacitor;
a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and
a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to a source line (SL), and a drain/source terminal coupled to the second terminal of the resistive memory element device, wherein the BL and SL are raised and lowered respectively or vice versa to write a state in the resistive memory element.

2. The apparatus of claim 1 further comprises control logic for operating the apparatus in DRAM mode or MRAM mode.

3. The apparatus of claim 2 , wherein the first transistor when turned ON in DRAM mode, charges the capacitor.

4. The apparatus of claim 3 , wherein the second transistor is turned OFF in DRAM mode.

5. The apparatus of claim 2 , wherein the first and second transistors are turned ON in MRAM mode.

6. The apparatus of claim 1 , wherein the capacitor is a MIM capacitor.

7. The apparatus of claim 1 , wherein the resistive memory element is one of:
Magnetic Tunnel Junction (MTJ) device;
Phase Change Memory (PCM) device;
Resistive RAM device; or
Conductive Bridging RAM.

8. An apparatus comprising:
a DRAM bit-cell comprising a first transistor having a gate terminal coupled to a first word line (WL) and a source/drain terminal coupled to a bit line (BL); and
an MRAM bit-cell integrated with the DRAM bit-cell, wherein the MRAM bit- cell comprises a second transistor having a gate terminal coupled to a second WL and a source/drain terminal coupled to a source line (SL), and the MRAM bit-cell comprising a resistive memory element, wherein the BL and SL are raised and lowered respectively or vice versa to write a state in the resistive memory element, and wherein a combination of DRAM bit-cell and MRAM bit-cell have no more than four control lines.

9. The apparatus of claim 8 , wherein the DRAM bit-cell includes a MIM capacitor.

10. The apparatus of claim 8 , wherein the DRAM bit-cell comprises:
a capacitor having a first terminal and a second terminal; and
the first transistor having a drain/source terminal coupled to a capacitor.

11. The apparatus of claim 10 , wherein the MRAM bit-cell comprises:
the resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor.

12. The apparatus of claim 11 , wherein the four control lines are the first WL, the second WL, SL, and BL.

13. The apparatus of claim 11 , wherein the resistive memory element is one of:
Magnetic Tunnel Junction (MTJ) device;
Phase Change Memory (PCM) device;
Resistive RAM device; or
Conductive Bridging RAM.

14. A system comprising:
a processor;
a memory coupled to the processor, the memory having an apparatus which comprises:

a capacitor having a first terminal and a second terminal;
a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and a drain/source terminal coupled to the first terminal of the capacitor;
a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and
a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to a source line (SL), and a drain/source terminal coupled to the second terminal of the resistive memory element device, wherein the BL and SL are raised and lowered respectively or vice versa to write a state in the resistive memory element; and
a wireless interface for allowing the processor to communicate with another device.

15. The system of claim 14 further comprises a display unit.

16. The system of claim 14 further comprises control logic for operating the apparatus in DRAM mode or MRAM mode.

17. A system comprising:
a processor;
a memory coupled to the processor, the memory having an apparatus which comprises:
a DRAM bit-cell comprising a first transistor having a gate terminal coupled to a first word line (WL) and a source/drain terminal coupled to a bit line (BL); and
an MRAM bit-cell integrated with the DRAM bit-cell, wherein the MRAM bit-cell comprises a second transistor having a gate terminal coupled to a second WL and a source/drain terminal coupled to a source line (SL), and the MRAM bit-cell comprising a resistive memory element, wherein the BL and SL are raised and lowered respectively or vice versa to write a state in the resistive memory element, and wherein a combination of DRAM bit-cell and MRAM bit-cell have no more than four control lines; and

a wireless interface for allowing the processor to communicate with another device.

18. The system of claim 17 further comprises a display unit.

19. The system of claim 17 , wherein the DRAM bit-cell includes a MIM capacitor.

Assignees

• Intel Corp

Inventors

• Manipatruni Sasikanth
• Young Ian A

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G11C13/0011

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title

• H01L27/228

  Electricity · mapped topic

• G11C14/0036 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title