Integrated assemblies having voids along regions of gates, and methods of forming conductive structures

Patent metadata

Field	Value
Publication number	US-12150292-B2
Application number	US-202217891480-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Dec 26, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.

First claim

I claim:

1. An integrated assembly, comprising:
a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions; the semiconductor-material-structure having a first side and an opposing second side;
a first conductive structure adjacent the first side and spaced from the first side by a first liner and a second liner; and
a second conductive structure adjacent the second side and spaced from the second side by an intervening region which includes a void.

2. The integrated assembly of claim 1 wherein the semiconductor material of the semiconductor-material-structure comprises silicon.

3. The integrated assembly of claim 1 wherein the first source/drain region is coupled with a digit line, and wherein the second source/drain region is coupled with a storage element.

4. The integrated assembly of claim 3 wherein the storage element is a capacitor.

5. The integrated assembly of claim 1 wherein the intervening region includes carbon-doped silicon dioxide between the semiconductor-material-structure and the void.

6. The integrated assembly of claim 1 wherein the first liner comprises an insulative material, and the second liner comprises carbon-doped silicon dioxide.

7. The integrated assembly of claim 1 wherein the first and second conductive structures each include a metal-containing-region directly against a doped-semiconductor-containing-region.

8. Integrated memory, comprising:
digit lines extending along a first direction;
semiconductor structures extending upwardly from the digit lines; the semiconductor structures including pillars; each of the pillars having an upper source/drain region and a channel region beneath the upper source/drain region; the semiconductor structures including lower source/drain regions beneath the channel regions; the lower source/drain regions being coupled with the digit lines;
storage elements coupled with the upper source/drain regions;
gate lines extending along a second direction which crosses the first direction; and
each of the gate lines having a first side and an opposing second side; a first set of the semiconductor structures being along the first side of an associated one of the gate lines and spaced from the first side by a first liner material comprising carbon-doped silicon dioxide and a second liner material, and a second set of the semiconductor structures being along the second side of said associated one of the gate lines, the channel regions within the second set of the semiconductor structures being spaced from the adjacent second side of said associated one of the gate lines by intervening regions which include voids.

9. The integrated memory of claim 8 wherein upper regions of the voids are capped by insulative material.

10. The integrated memory of claim 9 wherein the insulative material comprises silicon dioxide.

11. The integrated memory of claim 8 wherein the intervening regions include carbon-doped silicon dioxide.

12. The integrated memory of claim 8 wherein the gate lines cross over the digit lines and are spaced from the digit lines by intervening regions which include insulative regions comprising silicon nitride and carbon-doped silicon dioxide.

13. An integrated assembly, comprising:
linear features over a base; the linear features including digit lines and semiconductor-material-linear-configurations over the digit lines; the linear features extending along a first direction;
trenches extending into the linear features; the trenches extending along a second direction which crosses the first direction; the trenches patterning semiconductor material pillars from the semiconductor-material-linear-configurations; the pillars comprising upper source/drain regions, channel regions and lower source/drain regions coupled with the digit lines;
first liners comprising a first material within the trenches;
second liners over the first liners;
gate lines within the trenches and over second liners;
voids within the trench adjacent the gate lines; and
caps over the voids.

14. The integrated assembly of claim 13 wherein the first liners comprise carbon-doped silicon dioxide.

15. The integrated assembly of claim 13 wherein the second liners comprise silicon nitride.

16. The integrated assembly of claim 13 wherein portions of the lower source/drain regions are under the pillars.

17. The integrated assembly of claim 13 further comprising insulative material between the linear features.

18. The integrated assembly of claim 13 wherein the caps comprise silicon dioxide.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D

Classifications

• H10B12/488

  Word lines · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/48

  Data lines or contacts therefor · CPC title