Silicon recess etch and epitaxial deposit for shallow trench isolation (STI)

Patent metadata

Field	Value
Publication number	US-9911805-B2
Application number	US-201615349100-A
Country	US
Kind code	B2
Filing date	Nov 11, 2016
Priority date	Mar 15, 2013
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate including an active region;
a shallow trench isolation (STI) structure laterally surrounding the active region, wherein the semiconductor substrate includes an upper surface circumscribing outer sidewalls of the STI structure and a recessed surface circumscribed by inner sidewalls of the STI structure, the recessed surface having a height that is less than that of the upper surface, as measured from a bottom surface of the semiconductor substrate; and
a plurality of separate epitaxial silicon fins contacting the recessed surface and exhibiting an absence of germanium;
wherein the plurality of separate epitaxial silicon fins have upper surfaces which collectively follow a convex surface geometry, such that a first fin of the plurality of epitaxial silicon fins over a central region of the recessed surface has a first height and a second fin of the plurality of epitaxial silicon fins over a peripheral region of the recessed surface has a second height which is less than the first height.

2. The semiconductor device of claim 1 , wherein the convex surface geometry meets a plane corresponding to the upper surface of the semiconductor substrate at an angle of about 0.8 degrees.

3. The semiconductor device of claim 1 , wherein the plurality of separate epitaxial silicon fins has outer sidewalls in direct contact with the inner sidewalls of the STI structure.

4. The semiconductor device of claim 1 , further comprising:
a gate dielectric arranged over the epitaxial silicon fins; and
a conductive gate electrode arranged over the gate dielectric, the gate dielectric separating the conductive gate electrode from the epitaxial silicon fins.

5. The semiconductor device of claim 1 , wherein the epitaxial silicon fins are undoped.

6. The semiconductor device of claim 1 , wherein the plurality of epitaxial silicon fins are circumscribed by the inner sidewalls of the STI structure.

7. The semiconductor device of claim 1 , wherein the epitaxial silicon fins are made of intrinsic silicon.

8. A semiconductor device, comprising:
a semiconductor substrate including an active region;
a shallow trench isolation (STI) structure laterally surrounding the active region, wherein the semiconductor substrate includes an upper surface surrounding an outer perimeter of the STI structure and a recessed surface within an inner perimeter of the STI structure, the recessed surface having a height that is less than that of the upper surface, as measured from a bottom surface of the semiconductor substrate; and
an plurality of epitaxial silicon fins disposed on the recessed surface, wherein the epitaxial silicon fins collectively have an upper surface which is convex and which meets a plane that is parallel to the upper surface of the semiconductor substrate at an angle of about 0.8 degrees.

9. The semiconductor device of claim 8 , wherein the epitaxial silicon fins are surrounded by the inner sidewalls of the STI structure.

10. The semiconductor device of claim 9 , wherein the epitaxial silicon fins directly contact the recessed surface and exhibit an absence of germanium.

11. The semiconductor device of claim 8 , wherein the epitaxial silicon fins include an upturned tip that contacts a sidewall of the STI structure.

12. The semiconductor device of claim 8 , wherein the epitaxial silicon fins have outer sidewalls in direct contact with the inner sidewalls of the STI structure.

13. The semiconductor device of claim 8 , further comprising:
a gate dielectric arranged over the epitaxial silicon fins; and
a conductive gate electrode arranged over the gate dielectric, the gate dielectric separating the conductive gate electrode from the epitaxial silicon fins.

14. The semiconductor device of claim 8 , wherein the epitaxial silicon fins are undoped.

15. A semiconductor device, comprising:
a semiconductor substrate including an active area circumscribed by a peripheral region of the semiconductor substrate, wherein an upper surface of the active area is recessed relative to an upper surface of the peripheral region;
a plurality of epitaxial silicon fins disposed on the upper surface of the active area, wherein upper surfaces of the epitaxial silicon fins collectively follow a convex surface geometry; and
a shallow trench isolation (STI) structure laterally surrounding the active area and isolating the active area and epitaxial silicon fins from the peripheral region of the semiconductor substrate, wherein the epitaxial silicon fins include an up-turned tip that contacts a sidewall of the STI structure.

16. The semiconductor device of claim 15 , wherein the upper surface of the peripheral region is a substantially planar surface, and wherein the convex surface geometry meets a plane that is parallel to the upper surface of the peripheral region at an angle of about 0.8 degrees.

17. The semiconductor device of claim 15 , wherein the epitaxial silicon fins are circumscribed by the STI structure.

18. The semiconductor device of claim 15 , wherein the recessed upper surface of the active area is substantially planar, and wherein the epitaxial silicon fins directly contact the substantially planar recessed upper surface and exhibit an absence of germanium.

19. The semiconductor device of claim 15 , further comprising:
a gate dielectric arranged over the epitaxial silicon fins; and
a conductive gate electrode arranged over the gate dielectric, the gate dielectric separating the conductive gate electrode from the epitaxial silicon fins.

20. The semiconductor device of claim 15 , wherein the epitaxial silicon fins is intrinsic silicon.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry Hak Lay
• Young Bao Ru
• Wu Wei Cheng
• Chang Kong Pin
• Liang Chia Ming
• Hsu Meng Fang
• Fu Ching Feng
• Hung Shih Ting

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L27/0886

  Electricity · mapped topic

• H01L29/66651

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic