Methods of fabricating fin structures

Patent metadata

Field	Value
Publication number	US-9281402-B2
Application number	US-201414292443-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	Aug 22, 2006
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

First claim

What is claimed is:

1. A device, comprising:
a substrate comprising a trench formed into a surface of the substrate;
a first outcropping formed in the substrate, wherein the first outcropping is at least partially defined by a first side of the trench, and wherein the first outcropping comprises a first set of fin structures having a first channel formed there between; and
a second outcropping formed in the substrate, wherein the second outcropping is at least partially defined by a second side of the trench, wherein the second outcropping comprises a second set of tin structures having a second channel formed there between;
wherein the first outcropping and the second outcropping are formed substantially beneath an upper surface of the substrate.

2. The device of claim 1 , comprising:
first spacers formed on upper surfaces of the first set of fin structures; and
second spacers formed on upper surfaces of the second set of fin structures, wherein the first spacers and the second spacers are provided to mask the first set of fin structures and the second set of fin structures during an etching process.

3. The device of claim 1 , wherein the upper surfaces of the first outcropping and the second outcropping are recessed below the upper surface of the substrate.

4. The device of claim 1 , wherein the first outcropping comprises a first double fin field effect transistor (finFET).

5. The device of claim 1 , wherein the second outcropping comprises a second double fin field effect transistor (finFET).

6. The device of claim 1 , wherein each of the first set of fin structures and the second set of fin structures extends in an upward direction from the substrate and is at least partially separated by a dielectric material disposed inside the trench.

7. The device of claim 6 , wherein the dielectric material comprises a spin on dielectric (SOD) filler.

8. The device of claim 6 , wherein the first set of fin structures comprises a first fin and a second fin at least partially separated by the first channel, and wherein the dielectric material comprises a depth substantially equal to a depth of the first channel.

9. The device of claim 6 , wherein the second set of fin structures comprises a first fin and a second fin at least partially separated by the second channel, and wherein the dielectric material comprises a depth substantially equal to a depth of the second channel.

10. The device of claim 1 , wherein a height of the first set of fin structures and the second set of fin structures comprises a height within a range of approximately 500 Angstrom (Å) to 2,000 Å.

11. A device, comprising:
a substrate;
a trench formed in the substrate;
a plurality of outcroppings at least partially defined by each of the respective sides of the trench, wherein the plurality of outcroppings are recessed below an upper surface of the substrate; and
a plurality of couplets of fins extending substantially upwardly from the plurality of outcroppings, wherein each couplet of the plurality of couplets of fins comprises a channel formed between each fin of the couplet; and
a gate material disposed over and about the plurality of couplets of fins.

12. The device of claim 11 , wherein each of the plurality of couplets of fins is at least partially separated by a dielectric material disposed inside the trench.

13. The device of claim 12 , wherein the gate material is disposed atop the dielectric material, and wherein the gate material completely fills the trench.

14. The device of claim 11 , comprising a plurality of spacers formed on upper surfaces of each fin of each of the plurality of couplets of fins.

15. The device of claim 14 , wherein the plurality of spacers is provided to mask the plurality of couplets of fins during an etching process.

16. The device of claim 11 , comprising a contact material disposed on the gate material, and wherein the contact material comprises a layer of tungsten silicide.

17. A device, comprising:
a transistor, comprising:
a substrate;
a double fin structure recessed below an upper surface of the substrate, wherein the double fin structure comprises a first fin, a second fin, and a channel formed therebetween, and wherein the first fin and the second fin of the double fin structure extends substantially upwardly from a second surface of the substrate; and
a gate deposited on the double tin structure.

18. The device of claim 17 , comprising a plurality of double fin structures recessed below the upper surface of the substrate.

19. The device of claim 17 , wherein the double fin structure is formed atop an outcropping of the substrate, and wherein an upper surface of the outcropping is recessed below the upper surface of the substrate.

20. The device of claim 17 , comprising:
a first contact material formed on the gate; and
a second contact material formed on the substrate, wherein the second contact material is configured to couple a source or a drain of the transistor to the substrate.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Haller Gordon

Classifications

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title