Selection gate separation for 3D NAND

Patent metadata

Field	Value
Publication number	US-12148475-B2
Application number	US-202217705744-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Apr 1, 2021
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
at least one select-gate-for-drain (SGD) on a memory stack on a substrate, the memory stack comprising alternating word line and dielectric material;
at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material; and
at least one memory transistor in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

2. The semiconductor memory device of claim 1 , wherein the at least one select-gate-for-drain (SGD) transistor further comprises a first gate dielectric and the at least one memory transistor comprises a second gate dielectric, the first gate dielectric and the second gate dielectric comprising the same material.

3. The semiconductor memory device of claim 2 , wherein the first gate material is a gate-all-around (GAA) gate.

4. The semiconductor memory device of claim 1 , wherein the select-gate-for-drain (SGD) transistor and the memory transistor independently comprise one or more transistor layers selected from aluminum oxide (AlO), a blocking oxide, a trap material, a tunnel oxide, and a channel material.

5. The semiconductor memory device of claim 4 , further comprising a bit line pad on a drain side of the select-gate-for-drain (SGD) transistor and a self-aligned mask on the bit line pad.

6. The semiconductor memory device of claim 5 , wherein self-aligned mask comprises one or more of silicon nitride (SiN), aluminum oxide (AlO), hafnium, oxide (HfO), refractory metal, refractory metal silicide, refractory metal oxide, titanium nitride (TiN), tungsten (W), molybdenum (Mo), Tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), platinum (Pt), and osmium (Os).

7. The semiconductor memory device of claim 1 , wherein the word line comprises one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material.

8. The semiconductor memory device of claim 7 , wherein the metal is selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti), wherein the metal nitride is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN).

9. The semiconductor memory device of claim 7 , wherein the conductive metal compound is selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx).

10. The semiconductor memory device of claim 7 , wherein the semiconductor material is selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

11. The semiconductor memory device of claim 1 , further comprising at least one filled slit extending through the memory stack adjacent to the at least one select-gate-for-drain (SGD) transistor.

12. The semiconductor memory device of claim 11 , wherein the filled slit comprises an insulator material selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride.

13. The semiconductor memory device of claim 1 , wherein the substrate is a common source line, the common source line comprising a sacrificial layer, an oxide layer, and a poly-silicon layer.

14. A semiconductor memory device comprising:
at least one select-gate-for-drain (SGD) on a memory stack on a substrate, the memory stack comprising alternating word line and dielectric material;
a vertical string extending through the memory stack, the vertical string comprising at least one SGD transistor and at least one memory transistor;
a bit line pad on a top surface of the vertical string, the bit line pad having a first size; and
a self-aligned mask layer on a top surface of the bit line pad, the self-aligned mask layer having a second size, the second size from 1 nm to 50 nm larger than the first size.

15. The semiconductor memory device of claim 14 , wherein self-aligned mask comprises one or more of silicon nitride (SiN), aluminum oxide (AlO), hafnium, oxide (HfO), refractory metal, refractory metal silicide, refractory metal oxide, titanium nitride (TiN), tungsten (W), molybdenum (Mo), Tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), platinum (Pt), and osmium (Os).

16. A method of forming a semiconductor memory device having a three-dimensional vertical memory string including a select gate for drain (SGD) transistor and a memory transistor, the method comprising:
forming a select-gate-for-drain (SGD) gate on a top surface of memory stack, the memory stack comprising alternating layers of a first layer and a second layer on a substrate;
forming a memory string, the memory string extending through the select-gate-for-drain (SGD) gate and the memory stack;
forming a bit line pad on a top surface of the memory string;
forming a self-aligned mask on a top surface of the bit line pad;
forming a first opening in the select-gate-for-drain (SGD) gate;
filling the first opening with a dielectric material;
forming a slit extending from a top surface of the select-gate-for-drain (SGD) gate through the memory stack to the substrate;
removing the first layer to form a second opening; and
forming a word line in the second opening.

17. The method of claim 16 , wherein forming the memory string comprises:
patterning a memory hole extending from a top surface of the select-gate-for-drain (SGD) gate through the memory stack to a bottom surface of the substrate; and
depositing transistor layers in the memory hole, the transistor layers comprising one or more of an aluminum oxide (AlO) layer, a blocking oxide layer, a trap layer, a tunnel oxide layer, and a channel layer.

18. The method of claim 16 , wherein the self-aligned mask has a thickness in a range of from 1 nm to 100 nm and wherein the self-aligned mask overhangs the bit line pad in an amount in a range of from 1 nm to 50 nm.

19. The method of claim 16 , wherein the substrate is a common source line, the common source line comprising a sacrificial layer, an oxide layer, and a poly-silicon layer, and the method further comprises removing the sacrificial layer from the common source line to form a common source opening.

20. The method of claim 16 , further comprising forming word line contacts.

Assignees

• Applied Materials Inc

Inventors

• Kang Chang Seok
• Kitajima Tomohiko
• Lee Gill Yong
• Fu Qian
• Kang Sung-Kwan
• Koshizawa Takehito
• Fishburn Fredrick

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title