Accommodating imperfectly aligned memory holes

Patent metadata

Field	Value
Publication number	US-10319739-B2
Application number	US-201815882454-A
Country	US
Kind code	B2
Filing date	Jan 29, 2018
Priority date	Feb 8, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Methods of forming 3 -d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.

First claim

The invention claimed is:

1. A method of forming a 3-d flash memory cell, the method comprising:
placing a patterned substrate in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating silicon oxide and silicon nitride slabs and a vertical memory hole having sidewalls lined with a conformal ONO layer, wherein the conformal ONO layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, wherein the patterned substrate further comprises a first polysilicon layer formed on the conformal ONO layer, and wherein the vertical stack comprises a bottom portion and a top portion laterally misaligned to form a ledge;
forming a silicon nitride spacer on the ledge;
removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer;
removing a bottom portion of the conformal ONO layer using a gas-phase etch;
removing the silicon nitride spacer from the ledge using a gas-phase etch; and
forming a second polysilicon layer on the first polysilicon layer.

2. The method of claim 1 wherein the silicon nitride spacer completely covers the ledge but leaves a line-of-sight path from top to bottom of the vertical memory hole.

3. The method of claim 1 wherein forming the second polysilicon layer comprises making electrical contact between the first polysilicon layer, the second polysilicon layer and underlying silicon.

4. The method of claim 1 wherein removing the silicon nitride spacer comprises exciting both a fluorine precursor and an oxygen precursor in a remote plasma and flowing the plasma effluents into the substrate processing region housing the patterned substrate.

5. The method of claim 1 wherein the bottom portion and the top portion are laterally misaligned by more than 5 nm.

6. The method of claim 1 wherein removing the bottom portion of the conformal ONO layer is performed by exciting a hydrogen-containing precursor and a fluorine-containing precursor in a remote plasma to form plasma effluents.

7. The method of claim 6 wherein the plasma effluents are flowed into a substrate processing region through a showerhead, wherein the patterned substrate is in the substrate processing region and a temperature of the patterned substrate is greater than 95° C.

8. A method of forming a 3-d flash memory cell, the method comprising:
placing a patterned substrate in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating silicon oxide and silicon nitride slabs and a vertical memory hole having sidewalls lined with a conformal ONO layer, wherein the conformal ONO layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, wherein the patterned substrate further comprises a first polysilicon layer formed on the conformal ONO layer; wherein the vertical stack comprises a bottom portion and a top portion laterally misaligned to form a ledge;
forming sacrificial silicon oxide in the bottom portion of the vertical memory hole;
forming conformal silicon nitride on exposed portions of the first polysilicon layer uncovered by the sacrificial silicon oxide;
removing the sacrificial silicon oxide;
removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer;
removing a bottom portion of the conformal ONO layer using a gas-phase etch;
removing the conformal silicon nitride; and
forming a second polysilicon layer on the first polysilicon layer and making electrical contact between the second polysilicon layer and underlying silicon.

9. The method of claim 8 wherein the bottom portion and the top portion are laterally misaligned by more than 5 nm.

10. The method of claim 8 wherein removing the conformal silicon nitride comprises exciting both a fluorine precursor and an oxygen precursor in a remote plasma and flowing the plasma effluents into the substrate processing region housing the patterned substrate.

11. The method of claim 10 wherein the fluorine precursor comprises nitrogen trifluoride and the oxygen precursor comprises molecular oxygen (O 2 ).

12. A method of forming a 3-d flash memory cell, the method comprising:
forming a bottom portion of a compound stack of alternating silicon oxide and silicon nitride slabs;
forming a bottom portion of a memory hole through the bottom portion of the compound stack by patterning the bottom portion of the compound stack;
filling the bottom portion of the compound stack with doped silicon oxide;
forming a top portion of the compound stack of alternating silicon oxide and silicon nitride slabs;
forming a top portion of a memory hole through the top portion of the compound stack by patterning the top portion of the compound stack and exposing the doped silicon oxide; and
selectively removing the doped silicon oxide with a gas-phase etch which retains material in the alternating silicon oxide and silicon nitride slabs in each of the top portion and the bottom portion, wherein the bottom portion and the top portion of the compound stack are fluidly coupled and the top portion is laterally displaced from the bottom portion.

13. The method of claim 12 wherein the top portion is displaced from the bottom portion by at least 5 nm.

14. The method of claim 12 wherein the bottom portion comprises at least twenty pairs of slabs.

15. The method of claim 12 wherein the top portion comprises at least twenty pairs of slabs.

16. The method of claim 12 wherein the doped silicon oxide is doped with boron and/or phosphorus.

Assignees

• Applied Materials Inc

Inventors

• Purayath Vinod R

Classifications

• H10P72/0421

  for drying etching · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title