Charge-trap layer separation and word-line isolation for enhanced 3-D NAND structure

Patent metadata

Field	Value
Publication number	US-9960045-B1
Application number	US-201715423543-A
Country	US
Kind code	B1
Filing date	Feb 2, 2017
Priority date	Feb 2, 2017
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.

First claim

The invention claimed is:

1. A method of forming a plurality of nonvolatile memory cells, the method comprising:
forming a hole in a stack of alternating insulator layers and memory cell layers to expose an edge surface of each layer in the stack;
performing an isotropic etch process on the edge surface of each layer to selectively remove a portion of each memory cell layer and form first cavities between the insulator layers, wherein each memory cell layer includes an exposed portion adjacent to one of the first cavities;
oxidizing the exposed portion of each memory cell layer so that an oxide region is formed between insulator layers adjacent to the exposed portion, wherein a remaining portion of the memory cell layer is disposed between the insulator layers adjacent to the exposed portion;
depositing a charge trap material in the first cavities;
performing a selective etch process on the remaining portion of each memory cell layer to form second cavities that are disposed between the insulator layers; and
forming a control gate, within each of the second cavities, within at least one of the plurality of nonvolatile memory cells.

2. The method of claim 1 , wherein depositing the charge trap layer comprises:
conformally depositing the charge trap material on surfaces of the first cavities and the edge surfaces of the insulator layers; and
etching back the conformally deposited charge trap material to electrically separate the charge trap material in each of the first cavities from the charge trap material in adjacent first cavities.

3. The method of claim 2 , further comprising depositing a gate oxide layer on the edge surfaces of the insulator layers and the charge trap material disposed in the first cavities.

4. The method of claim 2 , further comprising depositing an electrically conductive material on the gate oxide to form a channel for the plurality of nonvolatile memory cells.

5. The method of claim 1 , further comprising removing the insulator layers in a selective etch process to form air gaps between the nonvolatile memory cells.

6. The method of claim 5 , wherein the removing the insulator layers comprises performing an isotropic etch process to expose surfaces of the gate oxide layer.

7. The method of claim 1 , wherein the memory cell layer comprises a sacrificial layer.

8. The method of claim 7 , wherein performing the selective etch process on the remaining portion of the memory cell layer comprises removing the remaining portion so that the second cavities are adjacent to the oxide region.

9. The method of claim 1 , wherein the memory cell layer comprises a layer of material that includes a semiconductor material and is electrically conductive.

10. The method of claim 9 , wherein forming the control gate comprises depositing a metal within each of the second cavities, wherein at least a portion of the formed oxide region is disposed between the deposited charge trap material and the deposited metal.

11. The method of claim 9 , wherein each second cavity is adjacent to a remaining portion.

12. A method of forming a plurality of nonvolatile memory cells, the method comprising:
forming a hole in a stack of alternating insulator layers and memory cell layers;
conformally depositing a charge trap layer on exposed surfaces in the hole;
forming a control gate, within each of the plurality of nonvolatile memory cells, from at least a portion of a memory cell layer;
performing a first selective etch process on an exposed surface of each insulator layer to remove the insulator layers and form an air gap between adjacent nonvolatile memory cells; and
performing a second selective etch process on portions of the charge trap layer that are each exposed to one of the air gaps, so that each nonvolatile memory cell includes a portion of the charge trap layer that is electrically separated from the portion of the charge trap layer in adjacent nonvolatile memory cells.

13. The method of claim 12 , wherein forming the hole into the stack of alternating insulator layers and memory cell layers comprises exposing an edge surface of each layer in the stack, and wherein the exposed surfaces in the hole are proximate the edge surface of each layer in the stack.

14. The method of claim 12 , further comprising, prior to conformally depositing the charge trap layer on exposed surfaces in the hole, conformally depositing a gate oxide layer on exposed surfaces in the hole.

15. The method of claim 14 , further comprising, prior to performing the second selective etch process portions of the charge trap layer that are each exposed to one of the air gaps, performing the second selective etch process on portions of the gate oxide layer that are each exposed to one of the air gaps.

Assignees

• Applied Materials Inc

Inventors

• Purayath Vinod Robert
• Ingle Nitin K

Classifications

• H01L21/28282 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title