Charge-trap layer separation and word-line isolation in a 3-D NAND structure

Patent metadata

Field	Value
Publication number	US-10468259-B2
Application number	US-201815966787-A
Country	US
Kind code	B2
Filing date	Apr 30, 2018
Priority date	Feb 2, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.

First claim

The invention claimed is:

1. A three-dimensional NAND device comprising:
a first nonvolatile memory cell comprising a gate oxide layer and a first section extending orthogonally from the gate oxide layer, the first section comprising:
a first charge trap region that contacts the gate oxide layer; and
a first control gate separated from the first charge trap region by a first blocking oxide region; and

a second nonvolatile memory cell comprising the gate oxide layer and a second section extending orthogonally from the gate oxide layer, wherein the first section and the second section are physically separated from each other by a gap, wherein the gap comprises an air gap and surfaces of the gate oxide layer are exposed to the air gap, the second section comprising:
a second charge trap region that contacts the gate oxide layer; and
a second control gate separated from the second charge trap region by a second blocking oxide region.

2. The device of claim 1 , wherein an insulator layer is disposed within the gap.

3. The device of claim 1 , wherein the first blocking oxide region and the second blocking oxide region are formed from a single blocking oxide layer.

4. The device of claim 3 , wherein the single blocking oxide layer is separated into the first blocking oxide region and the second blocking oxide region by the air gap.

5. The device of claim 1 , further comprising a diffusion barrier layer formed between the first control gate and the first blocking oxide region.

6. The device of claim 5 , wherein the diffusion barrier layer is made of a high-k dielectric material.

7. The device of claim 5 , further comprising a polysilicon channel formed adjacent the gate oxide layer.

8. The device of claim 7 , further comprising a filler material formed adjacent the polysilicon channel.

9. A three-dimensional NAND device comprising:
a first nonvolatile memory cell comprising a gate oxide layer and a first section extending orthogonally from the gate oxide layer, the first section comprising:
a first charge trap layer having a first surface and a second surface, the first surface of the first charge trap layer contacting a surface of the gate oxide layer, the second surface of the first charge trap layer contacting a first surface of a first blocking oxide layer;
a first diffusion barrier layer having a first surface and a second surface, the first surface of the first diffusion barrier layer contacting a second surface of the first blocking oxide layer;
a first conductive semiconductor layer having a first surface and a second surface, the first surface of the first conductive semiconductor layer contacting the second surface of the first diffusion barrier layer; and
a first control gate contacting the second surface of the first conductive semiconductor layer; and

a second nonvolatile memory cell comprising the gate oxide layer and a second section extending orthogonally from the gate oxide layer, wherein the first section and the second section are physically separated from each other by a gap, wherein the gap comprises an air gap and surfaces of the gate oxide layer are exposed to the air gap, the second section comprising:
a second charge trap layer having a first surface and a second surface, the first surface of the second charge trap layer contacting the surface of the gate oxide layer, the second surface of the second charge trap layer contacting a first surface of a second blocking oxide layer.

10. The device of claim 9 , further comprising:
a second diffusion barrier layer having a first surface and a second surface, the first surface of the second diffusion barrier layer contacting a second surface of the second blocking oxide layer;
a second conductive semiconductor layer having a first surface and a second surface, the first surface of the second conductive semiconductor layer contacting the second surface of the second diffusion barrier layer; and
a second control gate contacting the second surface of the second conductive semiconductor layer.

11. The device of claim 9 , wherein an insulator layer is disposed within the gap.

12. A three-dimensional NAND device comprising:
a first nonvolatile memory cell that includes:
a first charge trap layer having a first surface and a second surface, the first surface of the first charge trap layer contacting a surface of a gate oxide layer, the second surface of the first charge trap layer contacting a first surface of a first blocking oxide layer;
a first diffusion barrier layer having a first surface and a second surface, the first surface of the first diffusion barrier layer contacting a second surface of the first blocking oxide layer;
a first conductive semiconductor layer having a first surface and a second surface, the first surface of the first conductive semiconductor layer contacting the second surface of the first diffusion barrier layer; and
a first control gate contacting the second surface of the first conductive semiconductor layer; and

a second nonvolatile memory cell that is adjacent to the first nonvolatile memory cell and includes:
a second charge trap layer having a first surface and a second surface, the first surface of the second charge trap layer contacting the surface of the gate oxide layer, the second surface of the second charge trap layer contacting a first surface of a second blocking oxide layer, wherein the second charge trap layer and the first charge trap layer are physically separated from each other by a gap, wherein the gap comprises an air gap and surfaces of the gate oxide layer are exposed to the air gap.

13. The device of claim 10 , wherein the first blocking oxide layer and the second blocking oxide layer are formed from a single blocking oxide layer.

14. The device of claim 13 , wherein the single blocking oxide layer is separated into the first blocking oxide layer and the second blocking oxide layer by the air gap.

15. The device of claim 9 , wherein the first diffusion barrier layer is made of a high-k dielectric material.

16. The device of claim 9 , further comprising a polysilicon channel formed adjacent the gate oxide layer.

17. A method for forming a three-dimensional NAND device comprising:
forming a first nonvolatile memory cell comprising a gate oxide layer and a first section extending orthogonally from the gate oxide layer, the first section comprising:
forming a first charge trap region that contacts the gate oxide layer; and
forming a first control gate separated from the first charge trap region by a first blocking oxide region; and

forming a second nonvolatile memory cell comprising the gate oxide layer and a second section extending orthogonally from the gate oxide layer, wherein the first section and the second section are physically separated from each other by a gap, wherein the gap comprises an air gap and surfaces of the gate oxide layer are exposed to the air gap, the second section comprising:
forming a second charge trap region that contacts the gate oxide layer; and
forming a second control gate separated from the second charge trap region by a second blocking oxide region.

Assignees

• Applied Materials Inc

Inventors

• Purayath Vinod Robert
• Ingle Nitin K

Classifications

• H01L29/0649

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L21/28282 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title