Semiconductor device including power gating switches

Patent metadata

Field	Value
Publication number	US-12136595-B2
Application number	US-202017038561-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Dec 10, 2019
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

A semiconductor device includes first power supply lines arranged in a first direction and extended in a second direction, second power supply lines arranged in the second direction and extended in the first direction, power gating switches, and taps, Each of the power gating switches is connected with one of the first power supply lines and at least two of the second power supply lines. Each of the taps is connected with one of the first power supply lines or one of the second power supply lines. One of the power gating switches closest to a first power gating switch is a second power gating switch, one of the taps closest to the first power gating switch is a first tap, and at least one of the second power gating switch and the first tap is spaced from the first power gating switch in a third direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
first power supply lines arranged in a first direction and extending lengthwise in a second direction, the second direction being perpendicular to the first direction;
second power supply lines arranged in the second direction and extending lengthwise in the first direction;
power gating switches each connected with one of the first power supply lines and at least two of the second power supply lines; and
taps, each tap connected with one of the first power supply lines or one of the second power supply lines,
wherein a power gating switch closest to a first power gating switch from among the power gating switches is a second power gating switch, a tap closest to the first power gating switch from among the taps is a first tap, and at least one of the second power gating switch and the first tap is spaced apart from the first power gating switch in a third direction different from the first and second directions.

2. The semiconductor device of claim 1 , further comprising:
a logic circuit operating based on a supply voltage transferred through the second power supply lines,
wherein the power gating switches output the supply voltage to the second power supply lines, based on a gate control signal and a power supply voltage input from the first power supply lines.

3. The semiconductor device of claim 2 , further comprising:
third power supply lines arranged in the first direction and extending lengthwise in the second direction,
wherein the logic circuit operates based on a ground voltage transferred through the third power supply lines.

4. The semiconductor device of claim 2 , wherein each of the power gating switches includes:
a first diffusion area connected with the one of the first power supply lines;
a second diffusion area connected with one of the second power supply lines;
a gate pattern receiving the gate control signal; and
a third diffusion area doped to a different type from the first diffusion area and connected with the one of the first power supply lines.

5. The semiconductor device of claim 1 , wherein a size of each of the power gating switches is larger than a size of each of the taps.

6. The semiconductor device of claim 1 , wherein the first tap is interposed between the first power gating switch and the second power gating switch in the third direction.

7. The semiconductor device of claim 1 , wherein the first power gating switch is interposed between the second power gating switch and the first tap in the third direction.

8. The semiconductor device of claim 1 ,
wherein a third power gating switch closest to the first power gating switch in the first direction from among the power gating switches is disposed to have a first distance from the first power gating switch,
wherein a fourth power gating switch closest to the first power gating switch in the second direction from among the power gating switches is disposed to have a second distance smaller than the first distance from the first power gating switch, and
wherein the second power gating switch is disposed to have a third distance smaller than the second distance in the third direction from the first power gating switch.

9. The semiconductor device of claim 8 ,
wherein a distance at which the first power supply lines are arranged in the first direction is 6 μm to 9 μm,
wherein a distance at which the second power supply lines are arranged in the second direction is 0.4 μm to 0.8 μm,
wherein the first distance is 72 μm to 108 μm,
wherein the second distance is 9.6 μm to 19.2 μm, and
wherein a component of the third distance in the first direction is 6 μm to 9 μm, and a component of the third distance in the second direction is 0.8 μm to 1.6 μm.

10. The semiconductor device of claim 1 ,
wherein a second tap closest to the first tap from among the taps is spaced apart from the first tap in the third direction, and
wherein the first tap is interposed between the first power gating switch and the second tap in the third direction.

11. The semiconductor device of claim 10 ,
wherein a third tap closest to the first tap in the first direction from among the taps is disposed to have a first distance from the first tap,
wherein a fourth tap closest to the first tap in the second direction from among the taps is disposed to have a second distance smaller than the first distance from the first tap, and
wherein the second tap is disposed to have a third distance smaller than the second distance from the first tap.

12. The semiconductor device of claim 11 , wherein a distance at which the first power supply lines are arranged in the first direction is 6 μm to 9 μm,
wherein a distance at which the second power supply lines are arranged in the second direction is 0.4 μm to 0.8 μm,
wherein the first distance is 72 μm to 108 μm,
wherein the second distance is 9.6 μm to 19.2 μm, and
wherein a component of the third distance in the first direction is 6 μm to 9 μm, and a component of the third distance in the second direction is 0.8 μm to 1.6 μm.

13. The semiconductor device of claim 11 , wherein a distance at which the first power supply lines are arranged in the first direction is 6 μm to 9 μm,
wherein a distance at which the second power supply lines are arranged in the second direction is 0.4 μm to 0.8 μm,
wherein the first distance is 108 μm to 162 μm,
wherein the second distance is 14.4 μm to 28.8 μm, and
wherein a component of the third distance in the first direction is 9 μm to 13.5 μm, and a component of the third distance in the second direction is 1.2 μm to 2.4 μm.

14. A semiconductor device comprising:
a first power gating switch;
a second power gating switch closest to the first power gating switch in a first direction and spaced apart from the first power gating switch to have a first distance;
a third power gating switch closest to the first power gating switch in a second direction perpendicular to the first direction and spaced apart from the first power gating switch to have a second distance smaller than the first distance;
a fourth power gating switch closest to the first power gating switch in a third direction different from the second and first directions and spaced apart from the first power gating switch to have a third distance smaller than the second distance;
a first tap interposed between the first power gating switch and the second power gating switch;
a second tap interposed between the first power gating switch and the third power gating switch; and
a third tap interposed between the first power gating switch and the fourth power gating switch.

15. The semiconductor device of claim 14 , further comprising:
first power supply lines extending lengthwise in the second direction and outputting a first voltage to the first to fourth power gating switches and the first to third taps; and
second power supply lines extending lengthwise in the first direction and being input a second voltage, which is based on the first voltage, from the first to fourth power gating switches.

16. The semiconductor device of claim 15 , wherein each of the first to fourth power gating switches includes:
an N-well area;
a first diffusion area formed by highly doping the N-well area to a P-type, the first diffusion area being connected with one of the first power supply lines;
a second diffusion area formed by highly doping the N-well area to the P-type, the second diffusion area being connected with one of the second power supply lines;
a gate pattern disposed above the N-well area and receiving a gate con

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Jongsun
• An Junyeong
• Yi Dongyoun

Classifications

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L23/5286 Primary

  Electricity · mapped topic