Adaptive multi-tier power distribution grids for integrated circuits

Patent metadata

Field	Value
Publication number	US-10318694-B2
Application number	US-201715432431-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Nov 18, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

First claim

What is claimed is:

1. An integrated circuit module, comprising:
a first plurality of tiles,
a second plurality of tiles, wherein the integrated circuit module occupies a footprint on a semiconductor die, and wherein a first portion of the footprint includes the first plurality of tiles and a second portion of the footprint includes the second plurality of tiles;
a first power-grid tier for each tile in the first plurality of tiles; and
a second power-grid tier for each tile in the second plurality of tiles, wherein the first power-grid tier has a greater via density than the second power-grid tier for vias extending between metal layers defining power rails and ground rails for the integrated circuit module.

2. The integrated circuit module of claim 1 , wherein a plurality of power rails and ground rails for the first power-grid tier have a greater width than a width for a plurality of power rails and ground rails for the second power-grid tier.

3. The integrated circuit module of claim 1 , wherein a plurality of power rails and ground rails for the first power-grid tier have a smaller pitch than a pitch for a plurality of power rails and ground rails for the second power-grid tier.

4. The integrated circuit module of claim 1 , wherein the integrated circuit module comprises a single hard macro.

5. The integrated circuit module of claim 1 , wherein the first power-grid tier comprises a plurality of power-grid tiers having different via densities.

6. The integrated circuit module of claim 1 , wherein the first power-grid tier includes a greater number of power switches than the second power-grid tier.

7. The integrated circuit module of claim 4 , wherein a bulk of the single hard macro has a power-grid tier having a lowest density of vias.

Assignees

• Qualcomm Inc

Inventors

• Chung Joon Hyung
• Popovich Mikhail
• Reddy Gudoor

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title