Semiconductor memory device with a power gating circuit for reducing an instantaneous voltage drop

Patent metadata

Field	Value
Publication number	US-9627037-B2
Application number	US-201514978904-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Dec 24, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first power line configured to provide a first power supply voltage;
a first logic transistor;
a second logic transistor connected in series with the first logic transistor;
a first power transistor connected between the first power line and the first logic transistor; and
a second power transistor connected in parallel with the first power transistor,
wherein the first power transistor comprises:
a first source or drain connected to the first power line;
a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction; and
a gate receiving a power gating control signal, and
wherein a first source or drain of the second logic transistor is connected to the second power transistor, and
a second source or drain of the first logic transistor is connected to a second source or drain of the second logic transistor.

2. The semiconductor device of claim 1 , wherein the first source or drain and the second source or drain of the first power transistor are placed in parallel with each other and are spaced apart from each other,
at least part of the first source or drain of the first logic transistor is placed in common with at least part of the second source or drain of the first power transistor,
a second source or drain of the first logic transistor is placed in parallel with each other and is spaced apart from the first source or drain of the first logic transistor,
a gate of the first power transistor is placed between the first and second source or drain of the first power transistor, and
a gate of the first logic transistor is placed between the first source or drain and the second source or drain of the first logic transistor.

3. The semiconductor device of claim 1 , wherein a size of the first power transistor is at least twofold of that of the first logic transistor.

4. The semiconductor device of claim 1 , wherein
the second power transistor is connected between a second power line and the second logic transistor, and
the second power transistor comprises:
a first source or drain connected to the second power line; and
a second source or drain connected to the first source or drain of the second logic transistor using a shared semiconductor junction.

5. The semiconductor device of claim 4 , wherein the first power transistor is a P-channel metal-oxide semiconductor (PMOS) transistor, and the second power transistor is an N-channel metal-oxide semiconductor (NMOS) transistor.

6. A memory device comprising:
a memory cell connected to a first bit line pair;
a first precharge circuit configured to precharge the first bit line pair; and
a first power switch circuit comprising a first power transistor selectively supplying or cutting off a power supply voltage to the first precharge circuit,
wherein the first power transistor comprises:
a first source or drain to which the power supply voltage is applied;
a second source or drain connected to a first source or drain of a first precharge transistor in the first precharge circuit using a shared semiconductor junction; and
a gate receiving a power gating control signal.

7. The memory device of claim 6 , wherein the first bit line pair comprises a bit line and a bit-bar line, and
wherein the first precharge circuit comprises:
the first precharge transistor configured to apply a precharge voltage to the bit line;
a second precharge transistor connected between the bit line and the bit-bar line, wherein a voltage of the bit line is equal to a voltage of the bit-bar line; and
a third precharge transistor configured to apply the precharge voltage to the bit-bar line.

8. The memory device of claim 7 , wherein the first source or drain and the second source or drain of the first power transistor are placed in parallel with each other and are spaced apart from each other,
wherein at least part of the first source or drain of the first precharge transistor is placed in common with at least part of the second source or drain of the first power transistor,
wherein a second source or drain of the first precharge transistor is placed in parallel with and spaced apart from the first source or drain of the first precharge transistor,
wherein a gate of the first power transistor is placed between the first source or drain and the second source or drain of the first power transistor, and
wherein a gate of the first precharge transistor is placed between the first source or drain and the second source or drain of the first precharge transistor.

9. The memory device of claim 8 , wherein the first power switch circuit further comprises a second power transistor,
wherein the second power transistor comprises:
a first source or drain to which the power supply voltage is applied;
a second source or drain connected to a first source or drain of the third precharge transistor using a shared semiconductor junction; and
a gate configured to receive the power gating control signal.

10. The memory device of claim 9 , wherein the first source or drain and the second source or drain of the second power transistor are placed in parallel with each other and are spaced apart from each other,
wherein at least part of the first source or drain of the third precharge transistor is placed in common with at least part of the second source or drain of the second power transistor,
wherein a second source or drain of the third precharge transistor is placed in parallel with and spaced apart from the first source or drain of the third precharge transistor,
wherein a gate of the second power transistor is placed between the first source or drain and the second source or drain of the second power transistor, and
wherein a gate of the third precharge transistor is placed between the first source or drain and the second source or drain of the third precharge transistor.

11. The memory device of claim 10 , wherein the second source or drain of the first precharge transistor is placed in common with a first source or drain of the second precharge transistor, and
wherein the second source or drain of the third precharge transistor is placed in common with a second source or drain of the second precharge transistor.

12. The memory device of claim 9 , wherein each of the first and second power transistors is a P-channel metal-oxide semiconductor (PMOS) transistor.

13. The memory device of claim 9 , wherein a size of each of the first and second power transistors is at least twofold of that of each of the first through third precharge transistors.

14. The memory device of claim 9 , wherein the first precharge circuit further comprises:
a fourth precharge transistor applying the precharge voltage to the bit-bar line; and
a fifth precharge transistor applying the precharge voltage to the bit line,
wherein a first source or drain of the fourth precharge transistor is commonly connected to the bit-bar line and a gate of the fifth precharge transistor,
wherein a second source or drain of the fifth precharge transistor is commonly connected to the bit line and a gate of the fourth precharge transistor.

15. The memory device of claim 6 , further comprising:
a second bit line pair;
a second precharge circuit configured to precharge the second bit line pair; and
a second power switch circuit configured to selectively supply or cut off the power supply voltage to the second precharge circuit,
wherein the second precharge circuit is placed symmetrically to the first precharge circuit with respect to an axis, and
wherein the second pow

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tae Hyung
• Baeck Sang Yeop
• Kim Jae Young
• Kim Jin Sung

Classifications

• H03K17/687

  the devices being field-effect transistors · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• H03K17/063

  in field-effect transistor switches · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title