Wide pin for improved circuit routing

Patent metadata

Field	Value
Publication number	US-9536035-B2
Application number	US-201514809698-A
Country	US
Kind code	B2
Filing date	Jul 27, 2015
Priority date	Jun 3, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

First claim

What is claimed is:

1. An integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via, wherein the M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via.

2. The IC device of claim 1 , the M1 pin having a plurality of pin access points including at least one pin access point corresponding to a location of the via.

3. The system of claim 2 , wherein the at least one pin access point is located closest to a tip of the M1 pin.

4. The IC device of claim 1 , wherein the M1 pin extends vertically past the via a distance substantially equal to or greater than zero.

5. The IC device of claim 1 , further comprising a power rail, wherein a distance between the power rail and the M1 pin satisfies a side-to-side rule.

6. The IC device of claim 1 , wherein the M1 pin extends horizontally on both sides of the via a distance sufficient to satisfy the enclosure rule for the via.

7. The IC device of claim 6 , wherein the distance sufficient to satisfy the enclosure rule for the via is substantially equal to or greater than 15 nanometers.

8. A system for generating a layout of an integrated circuit (IC), the system comprising:
a processor; and
a non-transitory computer readable medium storing instructions, the instructions when executed by the processor causing the system to:
generate a layout for the IC, the layout comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via, wherein the M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via.

9. The system of claim 8 , the M1 pin having a plurality of pin access points including at least one pin access point corresponding to a location of the via.

10. The system of claim 9 , wherein the at least one pin access point is located closest to a tip of the M1 pin.

11. The system of claim 8 , wherein the M1 pin extends vertically past the via a distance substantially equal to or greater than zero.

12. The system of claim 8 , the standard cell further comprising an M2 power rail, wherein a distance between the M2 power rail and the M1 pin satisfies a side-to-side rule.

13. The system of claim 8 , wherein the M1 pin extends horizontally on both sides of the via a distance sufficient to satisfy the enclosure rule for the via.

14. The system of claim 13 , wherein the distance sufficient to satisfy the enclosure rule for the via is substantially equal to or greater than 15 nanometers.

15. A method for improving routing efficiency, the method comprising:
generating a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via, wherein the M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via.

16. The method of claim 15 , further comprising providing a plurality of pin access points for the M1 pin, including at least one pin access point utilized by the via.

17. The method of claim 16 , wherein the at least one pin access point utilized by the via is located closest to a tip of the M1 pin.

18. The method of claim 15 , wherein the M1 pin extends vertically past the via a distance substantially equal to or greater than zero.

19. The method of claim 15 , further comprising an M2 power rail, wherein a distance between the M2 power rail and the M1 pin satisfies a side-to-side rule.

20. The IC method of claim 15 , wherein the M1 pin extends horizontally on both sides of the via a distance sufficient to satisfy the enclosure rule for the via, wherein a distance sufficient to satisfy the enclosure rule for the via is substantially equal to or greater than 15 nanometers.

Assignees

• Globalfoundries Inc

Inventors

• Yuan Lei
• Kim Juhan
• Kye Jongwook
• Rashed Mahbub

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• G06F17/5077 Primary

  Physics · mapped topic