Method of forming conductive grid of integrated circuit

Patent metadata

Field	Value
Publication number	US-10360337-B2
Application number	US-201815903566-A
Country	US
Kind code	B2
Filing date	Feb 23, 2018
Priority date	Nov 22, 2017
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A method of forming an integrated circuit includes: forming a conductive grid on a semiconductor substrate; selecting a plurality of first conductive lines from a plurality of non-continuous conductive lines according to a first mask layer assigned to the plurality of first conductive lines; selecting a plurality of second conductive lines from the plurality of non-continuous conductive lines according to a second mask layer assigned to the plurality of second conductive lines, wherein the second mask layer different from the first mask layer, and the plurality of second conductive lines is electrically connected to the plurality of first conductive lines via the plurality of continuous conductive lines; and replacing the plurality of second conductive lines by a plurality of third conductive lines respectively, wherein the plurality of third conductive lines is assigned to the first mask layer.

First claim

What is claimed is:

1. A method of forming an integrated circuit:
forming a conductive grid on a semiconductor substrate, wherein the conductive grid has a plurality of continuous conductive lines arranged in a first direction on a first conductive layer and a plurality of non-continuous conductive lines arranged in a second direction on a second conductive layer;
selecting a plurality of first conductive lines from the plurality of non-continuous conductive lines;
selecting a plurality of second conductive lines from the plurality of non-continuous conductive lines; and
replacing the plurality of second conductive lines by a plurality of third conductive lines respectively when a cut-metal pattern is included in the plurality of first conductive lines and excluded from the plurality of second conductive lines, wherein the plurality of third conductive lines is assigned to a same mask layer as the plurality of the first conductive lines.

2. The method of claim 1 , wherein the first direction is orthogonal to the second direction, and the first conductive layer is different from the second conductive layer.

3. The method of claim 1 , wherein each of the plurality of second conductive lines comprises:
a first end and a second end, and the first end and the second end are not connected by the cut-metal pattern.

4. The method of claim 1 , wherein each of the plurality of third conductive lines comprises:
a first cut-metal pattern connected to a first end of the third conductive line; and
a second cut-metal pattern connected to a second end of the third conductive line.

5. The method of claim 1 , wherein each of the plurality of first conductive lines comprises:
a first cut-metal pattern connected to a first end of the first conductive line; and
a second cut-metal pattern connected to a second end of the first conductive line.

6. The method of claim 1 , wherein each of the plurality of third conductive lines is shorter than each of the plurality of second conductive lines.

7. The method of claim 1 , wherein a plurality of fourth conductive lines is disposed between the plurality of first conductive lines and the plurality of second conductive lines, the plurality of fourth conductive lines is assigned to a same mask layer as the plurality of second conductive lines, and the plurality of fourth conductive lines is not electrically connected to the plurality of first conductive lines and the plurality of second conductive lines.

8. The method of claim 7 , wherein each of the plurality of fourth conductive lines comprises a first end and a second end, and the first end and the second end are not connected by the cut-metal pattern.

9. The method of claim 7 , wherein a first continuous conductive line in the plurality of continuous conductive lines is electrically coupled to the plurality of first conductive lines and the plurality of second conductive lines, a second continuous conductive line in the plurality of continuous conductive lines is electrically coupled to the plurality of fourth conductive lines, and the first continuous conductive line is different from the second continuous conductive line.

10. The method of claim 1 , wherein the plurality of first conductive lines and the plurality of second conductive lines are assigned to different mask layers.

11. The method of claim 10 , wherein the plurality of second conductive lines is electrically connected to the plurality of first conductive lines via the plurality of continuous conductive lines.

12. A method of forming an integrated circuit:
forming a conductive grid on a semiconductor substrate, wherein the conductive grid has a plurality of continuous conductive lines arranged in a first direction on a first conductive layer and a plurality of non-continuous conductive lines arranged in a second direction on a second conductive layer;
selecting a plurality of first conductive lines from the plurality of non-continuous conductive lines;
selecting a plurality of second conductive lines from the plurality of non-continuous conductive lines;
assigning the plurality of first conductive lines and the plurality of second conductive lines to different mask layers;
disposing a cut-metal pattern on the plurality of second conductive lines overlapping a first group without overlapping a second group of the second conductive lines; and
removing end portions of the first group of the plurality of second conductive lines; and
reassigning the first group of the plurality of second conductive lines to a same mask layer as the plurality of first conductive lines.

13. The method of claim 12 , further comprising:
arranging a signal route passing through a space between the first group of the plurality of second conductive lines.

14. The method of claim 12 , wherein the plurality of second conductive lines is electrically connected to the plurality of first conductive lines via the plurality of continuous conductive lines.

15. The method of claim 12 , wherein a space between the plurality of first group after removal of the end portions is greater than a space between the second group of the plurality of second conductive lines.

16. The method of claim 12 , wherein a space between the first group of the plurality of second conductive lines is substantially equal to a space between the plurality of first conductive lines.

17. The method of claim 12 , wherein a length of the first group of the second conductive lines is substantially equal to a length of the first conductive line.

18. The method of claim 12 , wherein the conductive grid further includes a plurality of via structures to electrically connect the plurality of continuous conductive lines and the plurality of non-continuous conductive lines.

19. A system, comprising:
at least one processor, configured to execute program instructions which configure the at least one processor as a processing tool that perform operations comprising:
forming, by the processing tool, a conductive grid on a semiconductor substrate, wherein the conductive grid has a plurality of continuous conductive lines arranged in a first direction on a first conductive layer and a plurality of non-continuous conductive lines arranged in a second direction on a second conductive layer;
selecting, by the processing tool, a plurality of first conductive line and a plurality of second conductive line from the plurality of non-continuous conductive lines, wherein the plurality of first conductive line and the plurality of second conductive line are assigned to different mask layers; and
replacing, by the processing tool, the plurality of second conductive lines by a plurality of third conductive lines respectively when a cut-metal pattern overlaps the plurality of first conductive lines and is separated from the plurality of second conductive lines from a top view perspective, wherein the plurality of third conductive lines is assigned to a same mask layer as the plurality of the first conductive lines.

20. The system of claim 19 , further comprising:
a display tool, configured to display the plurality of first conductive lines with a first color and the plurality of second conductive lines with a second color different from the first color.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Biswas Hiranmay
• Yang Kuo-Nan
• Wang Chung-Hsing

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• H01L27/0207

  Electricity · mapped topic