Standard cell and an integrated circuit including the same

Patent metadata

Field	Value
Publication number	US-12125787-B2
Application number	US-202017037569-A
Country	US
Kind code	B2
Filing date	Sep 29, 2020
Priority date	Apr 11, 2017
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of standard cells, each comprising at least one active region extending in a first direction, at least one gate line extending in a second direction and at least one pattern formed in a first conductive layer; and
a plurality of power rails extending in the first direction along boundaries of the plurality of standard cells,
wherein a first power rail of the plurality of power rails comprises a first pattern formed in a second conductive layer upper than the first conductive layer and extending in the first direction along a boundary of a first standard cell of the plurality of standard cells, and
a length of the first pattern in the first direction is less than a length of the first standard cell in the first direction,
wherein the first standard cell comprises a plurality of second patterns formed in the second conductive layer and extending in the second direction,
each of the plurality of second patterns has a first width and is spaced apart from an adjacent second pattern by a first distance in the first direction, and
the length of the first pattern is greater than a sum of the first width and the first distance, and
at least one of the plurality of second patterns is spaced apart from the first pattern in the second direction.

2. The integrated circuit of claim 1 , wherein the first power rail further comprises a first conductive line formed in a third conductive layer higher than the second conductive layer and extending in the first direction throughout the first power rail.

3. The integrated circuit of claim 2 , wherein the first power rail further comprises:
a second conductive line formed in the first conductive layer lower than the second conductive layer and extending in the first direction throughout the first power rail;
a first via electrically connecting the first pattern and the first conductive line; and
a second via electrically connecting the first pattern and the second conductive line.

4. The integrated circuit of claim 3 , wherein at least one of the first via and the second via has a bar type via.

5. The integrated circuit of claim 1 , wherein a second power rail of the plurality of power rails is adjacent to the first power rail,
a second standard cell of the plurality of standard cells has a first boundary and a second boundary extending in the first direction and overlapped with the first power rail and the second power rail respectively in a vertical direction orthogonal to the first direction and the second directions, and
the first power rail and the second power rail are configured to provide different supply voltages respectively to the second standard cell.

6. The integrated circuit of claim 5 , wherein the first power rail comprises a pattern formed in the second conductive layer and extending in the first direction throughout the first boundary, and
the second power rail comprises a pattern formed in the second conductive layer and extending in the first direction throughout the second boundary.

7. The integrated circuit of claim 5 , wherein the second standard cell comprises a second pattern and a third pattern formed in the second conductive layer and extending in the second direction,
the second pattern overlaps with the first power rail in the vertical direction and is insulted from the first power rail, and
the third pattern overlaps with the second power rail in the vertical direction and is insulated from the second power rail, and
the third pattern overlaps with the second power rail in the vertical direction and is insulated from the secodn power rail.

8. The integrated circuit of claim 5 , wherein the first power rail comprises a pattern formed in the second conductive layer and extending in the first direction throughout the first boundary,
the second standard cell comprises a second pattern formed in the second conductive layer and extending in the second direction, and
the second pattern overlaps with the second power rail in the vertical direction and is insulated from the second power rail.

9. An integrated circuit, comprising:
a first power rail and a second power rail extending in a first direction and configured to provide different supply voltages respectively to a first standard cell;
at least one active region extending in the first direction between the first power rail and the second power rail;
at least one gate line extending in a second direction between the first power rail and the second power rail; and
a first pattern passing in the second direction between a pair of patterns included in the first power rail and configured to transfer an input signal or an output signal of the first standard cell, wherein the pair of patterns is formed in a same layer as the first pattern; and
a second pattern extending in the second direction between the first and second power rails, first and second ends of the second pattern being opposite each other along the second direction, the first end being adjacent to and facing the first power rail in the second direction, the second end being adjacent to and facing the second power rail in the second direction, the first and second ends being separated from and located between the first and second power rails in the second direction, and wherein the first and second ends of the second pattern are disposed in the same layer as the first pattern.

10. The integrated circuit of claim 9 , wherein the first power rail further comprises a first conductive line formed in a first conductive layer and a second conductive line formed in a third conductive layer, and
the first pattern is formed in a second conductive layer between the first conductive layer and the third conductive layer.

11. The integrated circuit of claim 10 , further comprising:
a third pattern formed in the first conductive layer, extending in the first direction and configured to transfer an input signal or an output signal of the first standard cell,
wherein a width of the second pattern is less than a width of the first conductive line.

12. The integrated circuit of claim 11 , wherein the third pattern is connected to a semiconductor device included in the first standard cell through a contact and/or a via.

13. The integrated circuit of claim 10 , further comprising:
a third pattern formed in the third conductive layer, extending in the first direction and configured to transfer an input signal or an output signal of the first standard cell,
wherein a width of the second pattern is less than a width of the second conductive line.

14. The integrated circuit of claim 9 , wherein the first pattern passes in the second direction between a pair of patterns included in the second power rail.

15. The integrated circuit of claim 9 , wherein the pair of patterns include a second pattern extending in the first direction along a boundary of the first standard cell, and
a length of the second pattern in the first direction is less than a length of the first standard cell in the first direction.

16. An integrated circuit, comprising:
a first power rail and a second power rail extending in a first direction and configured to provide different supply voltages respectively to a first standard cell;
at least one active region extending in the first direction between the first power rail and the second power rail;
at least one gate line extending in a second direction between the first power rail and the second power rail;
a first pattern passing in the second direction between a pair of patterns included in the first power rail and configured

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jae-Boong
• Do Jung-Ho
• Song Tae-Joong
• Lee Seung-Young
• Jung Jong-Hoon
• Yu Ji-Su

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/981

  Power supply lines · CPC title