Integrated circuit and method of designing layout of the same

Patent metadata

Field	Value
Publication number	US-9734276-B2
Application number	US-201514875910-A
Country	US
Kind code	B2
Filing date	Oct 6, 2015
Priority date	Oct 22, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method of designing a layout of an integrated circuit (IC) includes: preparing a standard cell library that stores a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including a plurality of conductive lines that extend in a first direction, placing the first standard cell and the second standard cell to be adjacent to each other in a first boundary parallel to the plurality of conductive lines, and generating a decoupling capacitor by using at least one first conductive line of the plurality of conductive lines when a same voltage is applied to a first pattern adjacent to the first boundary in the first standard cell and a second pattern adjacent to the first boundary in the second standard cell, the at least one first conductive line being adjacent to the first boundary.

First claim

What is claimed is:

1. A method of designing a layout of an integrated circuit (IC) in an electronic processor, the method comprising:
preparing, using a processor, a standard cell library that stores a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including a plurality of conductive lines that extend in a first direction;
placing, using the processor, the first standard cell and the second standard cell to be adjacent to each other at a first boundary parallel to the plurality of conductive lines; and
generating, using the processor, a decoupling capacitor by using at least one first conductive line of the plurality of conductive lines when a same voltage is to be applied to a first conductive pattern adjacent to the first boundary in the first standard cell and to a second conductive pattern adjacent to the first boundary in the second standard cell, wherein the at least one first conductive line being adjacent to the first boundary.

2. The method of claim 1 , wherein the at least one first conductive line is disposed on the first boundary.

3. The method of claim 1 , further comprising insulating the first standard cell from the second standard cell by using the at least one first conductive line as a dummy line when different voltages are to be applied to the first conductive pattern and the second conductive pattern.

4. The method of claim 1 , wherein at least one of the first standard cell and the second standard cell includes a cutting layer disposed on the first boundary, the cutting layer being configured to insulate the first standard cell from the second standard cell; and the generating of a decoupling capacitor further comprises removing the cutting layer between the first pattern and the second pattern to generate the decoupling capacitor when the same voltage is to be applied to the first pattern and the second pattern.

5. The method of claim 4 , wherein the first standard cell further includes first fins that extend in a second direction substantially perpendicular to the first direction; the second standard cell further includes second fins that extend in the second direction; and the cutting layer is disposed to insulate the first fins included in the first standard cell from the second fins included in the second standard cell.

6. The method of claim 5 , wherein the first pattern is a first contact pattern disposed on some of the first fins; the second pattern is a second contact pattern disposed on some of the second fins; and a first contact fin of the first fins, a second contact fin of the second fins, and the at least one first conductive line implement a transistor corresponding to the decoupling capacitor, the first contact fins and the second contact fins being respectively connected to the first contact pattern and the second contact pattern.

7. The method of claim 4 , further comprising maintaining the cutting layer between the first pattern and the second pattern such that the first conductive line becomes a dummy line when different voltages are to be applied to the first pattern and the second pattern.

8. The method of claim 4 , wherein the at least one of the first standard cell and the second standard cell further includes an additive cutting layer disposed on a second boundary opposite to the first boundary.

9. The method of claim 1 , further comprising generating a cutting layer between the first pattern and the second pattern after the placing of the first standard cell and the second standard cell when different voltages are to be applied to the first pattern and the second pattern, the cutting layer being configured to insulate the first standard cell from the second standard cell.

10. The method of claim 9 , wherein the first standard cell further includes first fins that extend in a second direction substantially perpendicular to the first direction; the second standard cell further includes second fins that extend in the second direction; and the cutting layer is disposed to insulate the first fins included in the first standard cell from the second fins included in the second standard cell.

11. The method of claim 10 , wherein the first pattern is a first contact pattern disposed on some of the first fins; the second pattern is a second contact pattern disposed on some of the second fins; and a first contact fin of the first fins, a second contact fin of the second fins, and the at least one first conductive line implement a transistor corresponding to the decoupling capacitor, the first contact fin and second contact fin being respectively connected to the first contact pattern and the second contact pattern.

12. The method of claim 9 , further comprising generating an additive cutting layer disposed on a second boundary opposite to the first boundary with respect to at least one of the first pattern and the second pattern after the placing of the first standard cell and the second standard cell.

13. The method of claim 1 , wherein the same voltage applied to the first pattern and the second pattern is a power supply voltage or a ground voltage.

14. The method of claim 1 , wherein the plurality of conductive lines correspond to a plurality of gate electrodes.

15. The method of claim 1 , further comprising designing the IC such that the first conductive line floats.

16. A method of designing an integrated circuit using a design tool that includes a processor, the method comprising:
selecting, using the processor, a first standard cell and a second standard cell from a standard cell library and placing them adjacent to each other, wherein the first standard cell and the second standard cell include conductive lines adjacent to and parallel to a boundary formed between these two standard cells by their adjacent placement and conductive contact patterns parallel to the boundary;
determining, using the processor, whether a same voltage is to be applied to conductive contact patterns in each standard cell according to a design of the integrated circuit; and
forming, using the processor, a decoupling capacitor by using the conductive lines when a same voltage is to be applied to the conductive contact patterns in each standard cell.

17. The method of claim 16 , wherein the processor designs the conductive contact patterns to be connected to a power supply voltage.

18. The method of claim 16 , wherein the processor designs the conductive contact patterns to be connected to a ground.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jin-Tae
• Kim Chang-Beom

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5072 Primary

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic

• H01L27/0207

  Electricity · mapped topic