Method and layout of an integrated circuit

Patent metadata

Field	Value
Publication number	US-9653393-B2
Application number	US-201314104730-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Dec 12, 2013
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

An integrated circuit layout includes a first metal line, a second metal line, at least one first conductive via and a first conductive segment. The first metal line is formed along a first direction. The at least one first conductive via is disposed over the first metal line. The second metal line is disposed over at least one first conductive via and is in parallel with the first metal line. The first conductive segment is formed on one end of the second metal line.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first metal line having a length and a width, the length of the first metal line formed along a first direction;
at least one first conductive via disposed over the first metal line;
a second metal line having a length and a width, the length of the second metal line formed along the first direction, the second metal line disposed over the at least one first conductive via and in parallel with the first metal line;
a first conductive segment formed on a first end of the second metal line, a width of the first conductive segment greater than the width of the first metal line and the width of the second metal line; and
a second conductive segment formed on a second, opposing end of the second metal line, a width of the second conductive segment greater than the width of the first metal line and the width of the second metal line.

2. The integrated circuit of claim 1 , wherein a top boundary of the first conductive segment is aligned with a top boundary of the second metal line.

3. The integrated circuit of claim 1 , wherein a bottom boundary of the first conductive segment is aligned with a bottom boundary of the second metal line.

4. The integrated circuit of claim 1 , wherein the length of the second metal line is equal to or larger than a summation of a length of the first conductive segment and the second conductive segment.

5. The integrated circuit of claim 1 , wherein a width of the first conductive segment is equal to or larger than a width of the second conductive segment.

6. The integrated circuit of claim 1 , wherein a length of the first conductive segment is equal to or larger than a length of the second conductive segment.

7. An integrated circuit, comprising:
a first metal line formed in a first metal layer, the first metal line having a length and a width, the length of the first metal line formed along a first direction;
a conductive via disposed over the first metal line;
a second metal line formed in a second metal layer over the conductive via, the second metal line having a length and a width, the length of the second metal line formed along the first direction;
a first conductive segment extending from one end of the second metal line, the first conductive segment having a width greater than the width of the second metal line; and
a second conductive segment extending from another end of the second metal line, the second conductive segment having a width greater than the width of the second metal line.

8. The integrated circuit of claim 7 , wherein a top boundary of the first conductive segment is aligned with a top boundary of the second metal line.

9. The integrated circuit of claim 7 wherein the length of the second metal line is equal to or larger than a summation of a length of the first conductive segment and the second conductive segment.

10. The integrated circuit of claim 7 , wherein the second metal line together with one of the first conductive segment and the second conductive segment form a H-like shape metal line in the second metal layer.

11. An integrated circuit comprising:
a first metal line formed in a first metal layer, the first metal line having a length and a width, the length of the first metal line formed along a first direction;
a conductive via above the first metal line;
a second metal line formed in a second metal layer above the conductive via, the second metal line having a length and a width, the length of the second metal line formed along the first direction;
a first conductive segment extending from a first lateral extent of the second metal line, the first conductive segment having a width greater than the width of the second metal line; and
a second conductive segment extending from a second lateral extent of the second metal line, the second conductive segment having a width greater than the width of the second metal line.

12. The integrated circuit of claim 11 , wherein an upper extent of the first conductive segment is aligned with an upper extent of the second metal line.

13. The integrated circuit of claim 12 , wherein a lower extent of the first conductive segment is aligned with a lower extent of the second metal line.

14. The integrated circuit of claim 13 , wherein the length of the second metal line is greater than or equal to an aggregate length of the first conductive segment and the second conductive segment.

15. The integrated circuit of claim 14 , wherein a width of the first conductive segment is greater than or equal to a width of the second conductive segment.

16. The integrated circuit of claim 15 , wherein a length of the first conductive segment is greater than or equal to a length of the second conductive segment.

17. The integrated circuit of claim 16 , wherein the second metal line and one of the first conductive segment or the second conductive segment form an orthogonal shape in the second metal layer.

18. The integrated circuit of claim 17 , wherein the second metal line and the first conductive segment form a H-like shape metal line in the second metal layer.

19. The integrated circuit of claim 17 , wherein the second metal line and the second conductive segment form a H-like shape metal line in the second metal layer.

20. The integrated circuit of claim 11 , wherein the second lateral extent opposes the first lateral extent.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Yu
• Tien Li-Chun
• Zhuang hui-zhong
• Chiang Ting-Wei
• Tseng Hsiang-Jen

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H01L2924/00

  Electricity · mapped topic