3d semiconductor structure and device

Patent metadata

Field	Value
Publication number	US-2017301667-A1
Application number	US-201715482761-A
Country	US
Kind code	A1
Filing date	Apr 8, 2017
Priority date	Mar 12, 2013
Publication date	Oct 19, 2017
Grant date	—

Abstract

A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines.

First claim

We claim:

1 . A 3D structure, the structure comprising:
a first stratum overlaid by a second stratum, said second stratum is less than two microns thick,
wherein said first stratum comprises an array of memory cells comprising at least four rows of memory cells, each of said rows is controlled by a bit-line,
wherein said array of memory cells comprises a plurality of columns of memory cells, each of said columns is controlled by a word-line, and
wherein said second stratum comprises memory control circuits directly connected to said bit-lines and said word-lines.

2 . The 3D structure according to claim 1 ,
wherein said 3D structure is designed such that it could be processed to form a first 3D device and a second 3D device, wherein said first 3D device comprises many more memory cells than said second 3D device.

3 . The 3D structure according to claim 1 ,
wherein said 3D structure is designed to perform self-test and repair partly by activating a built-in redundancy.

4 . The 3D structure according to claim 1 ,
wherein said second stratum is connected with a face to face connection to said first stratum.

5 . The 3D structure according to claim 1 , further comprising:
a wireless connection channel to at least one external device.

6 . The 3D structure according to claim 1 ,
wherein said first stratum comprises a layer select to support selecting said first stratum.

7 . The 3D structure according to claim 1 , further comprising:
vias,
wherein said directly connected comprises said vias, and
wherein said vias have a radius of less than 400 nm.

8 . A 3D structure, the structure comprising:
a first stratum overlaid by a second stratum, said second stratum is less than two microns thick,
wherein said first stratum comprises an array of memory cells comprising at least four rows of memory cells, each of said rows is controlled by a bit-line,
wherein said array of memory cells comprises a plurality of columns of memory cells, each of said columns is controlled by a word-line,
wherein said second stratum comprises memory control circuits directly connected to control said memory cells,
wherein said 3D structure is designed such that it could be processed to form a first 3D device and a second 3D device, and
wherein said first 3D device comprises many more memory cells than said second 3D device.

9 . The 3D structure according to claim 8 ,
wherein said 3D structure is designed to perform self-test and repair partly by activating a built-in redundancy.

10 . The 3D structure according to claim 8 ,
wherein said second stratum is connected with a face to face connection to said first stratum.

11 . The 3D structure according to claim 8 , further comprising:
a wireless connection channel to at least one external device.

12 . The 3D structure according to claim 8 ,
wherein said first stratum comprises a layer select to support selecting said first stratum.

13 . The 3D structure according to claim 8 , further comprising:
vias,
wherein said directly connected comprises said vias, and
wherein said vias have a radius of less than 400 nm.

14 . The 3D structure according to claim 8 ,
wherein said second stratum comprises said memory control circuits directly connected to said bit-lines and said word-lines.

15 . A 3D structure, the structure comprising:
a first stratum overlaid by a second stratum, said second stratum is less than two microns thick,
wherein said first stratum comprises an array of memory cells comprising at least four rows of memory cells, each of said rows is controlled by a bit-line,
wherein said array of memory cells comprises a plurality of columns of memory cells, each of said columns is controlled by a word-line,
wherein said second stratum comprises memory control circuits directly connected to control said memory cells, and
wherein said 3D structure is designed to perform self-test and repair itself partly by activating a built-in redundancy.

16 . The 3D structure according to claim 15 ,
wherein said second stratum comprises memory control circuits directly connected to said bit-lines and said word-lines.

17 . The 3D structure according to claim 15 ,
wherein said second stratum is connected with a face to face connection to said first stratum.

18 . The 3D structure according to claim 15 , further comprising:
a wireless connection channel to at least one external device.

19 . The 3D structure according to claim 15 ,
wherein said first stratum comprises a layer select to support selecting said first stratum.

20 . The 3D structure according to claim 15 , further comprising:
vias,
wherein said directly connected comprises said vias, and
wherein said vias have a radius of less than 400 nm.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Wurman Zeev

Classifications

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title