Semiconductor device having structure for improving voltage drop and device including the same

Patent metadata

Field	Value
Publication number	US-2017018504-A1
Application number	US-201615208639-A
Country	US
Kind code	A1
Filing date	Jul 13, 2016
Priority date	Jul 16, 2015
Publication date	Jan 19, 2017
Grant date	—

Abstract

A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction. The first direction is perpendicular to the second direction. The first voltage is one of a ground voltage and a power source voltage and the second voltage is the other voltage.

First claim

1 . A semiconductor device comprising:
a semiconductor substrate; and a plurality of metal layers disposed one above another on the semiconductor substrate, wherein each of at least one of the metal layers comprises: a plurality of first power rails dedicated for connection to a first voltage and each of which extend longitudinally in a first direction; a plurality of second power rails dedicated for connection to a second voltage and each of which extends longitudinally in the first direction; and a first conductor which is integral with each of the first power rails at first ends of the first power rails, respectively, and spans the first power rails in a second direction.

2 . The semiconductor device of claim 1 , wherein said one of the metal layers further comprises a second conductor which is integral with each of the first power rails at second ends of the first power rails, respectively, and spans the power rails in the second direction.

3 . The semiconductor device of claim 1 , wherein the first power rails and the first conductor are disposed at the same level in the device above the substrate.

4 . The semiconductor device of claim 1 , wherein the first direction is perpendicular to the second direction.

5 . The semiconductor device of claim 1 , wherein the first power rails are alternately disposed with the second power rails in a horizontal direction parallel to an upper surface of the substrate.

6 . The semiconductor device of claim 1 , further comprising a first logic gate disposed at an upper portion of the semiconductor substrate and electrically connected to one of the first power rails and one of the second power rails.

7 . The semiconductor device of claim 6 , further comprising a second logic gate disposed at an upper portion of the semiconductor substrate and electrically connected to said one of the second power rails and another one of the first power rails.

8 . The semiconductor device of claim 1 , further comprising a hard macro disposed beside the first conductor.

9 . The semiconductor device of claim 1 , further comprising a plurality of vias including a plurality of first vias and a plurality of second vias, and
wherein the metal layers comprise a second metal layer disposed above the first metal layer and including a third power rail dedicated for connection to the first voltage, and a fourth power rail dedicated for connection to the second voltage, the plurality of first vias which electrically connect the first power rails with the third power rail such that the third power rail provides the first voltage to the first power rails, and the plurality of second vias which electrically connect the second power rails with the fourth power rail such that the fourth power rail provides the second voltage to the second power rails.

10 . The semiconductor device of claim 9 , wherein each of the third power rail and the fourth power rail extend in the second direction.

11 . The semiconductor device of claim 9 , wherein at least one of the metal layers is interposed between the first metal layer and the second metal layer.

12 - 18 . (canceled)

19 . A semiconductor device comprising:
a semiconductor substrate; active electronic elements disposed at an upper portion of the semiconductor substrate as arrayed in first and second directions each parallel to an upper surface of the semiconductor substrate; a plurality of first power rails each of which extends longitudinally in the first direction across the array of active electronic elements; a plurality of second power rails each of which extends longitudinally in the first direction across the array of active electronic elements; a conductor that is integral with each of the first power rails at first ends of the first power rails, respectively; a third power rail disposed above the first power rails and extending across the first power rails in the second direction; and a first set of vias electrically connecting the third power rail to the first power rails, each of the active electronic elements is electrically connected to a respective one of the first power rails and a respective one of the second power rails.

20 . The semiconductor device of claim 19 , further comprising a second conductor that is integral with each of the first power rails at second ends of the first power rails, respectively, and
wherein the third power rail is located in the first direction between the second conductor and the array of active electronic elements.

21 . The semiconductor device of claim 19 , wherein the first and second power rails are alternately disposed in the second direction.

22 . The semiconductor device of claim 19 , wherein the conductor is contiguous with the first power rails, and
the first power rails, the second power rails and the conductor have coplanar upper and lower surfaces and collectively constitute a first metal layer.

23 . The semiconductor device of claim 22 , further comprising at least one other metal layer vertically interposed between the third power rail and the first metal layer.

24 . The semiconductor device of claim 19 , further comprising a fourth power rail disposed above the second power rails and extending across the second power rails in the second direction; and
a second set of vias electrically connecting the fourth power rail to the second power rails, and wherein the array of the active electronic elements is located in the first direction between the third power rail and the conductor.

25 . The semiconductor device of claim 24 , wherein the fourth power rail has upper and lower surfaces coplanar with upper and lower surfaces of the third power rail.

26 . A semiconductor system comprising:
a semiconductor substrate; active electronic elements disposed at an upper portion of a first region of the semiconductor substrate as arrayed in first and second directions each parallel to an upper surface of the semiconductor substrate; a hard macro disposed at an upper portion of a second region of the semiconductor substrate; metal layers disposed on the semiconductor substrate at a plurality of different levels each above the levels of the logic gates and the hard macro; a first set of vias; and a second set of vias, and wherein a first one of the metal layers comprises a plurality of first power rails each of which extends longitudinally in the first direction across the array of active electronic elements, a plurality of second power rails each of which extends longitudinally in the first direction across the array of active electronic elements, and a conductor integral with each of the first power rails at first ends of the first power rails, respectively, another of the metal layers is disposed above the first metal layer and includes a third power rail extending across the first power rails in the second direction, and a fourth power rail extending across the second power rails in the second direction, the first set of vias electrically connects the third power rail to the first power rails, the second set of vias electrically connects the fourth power rail to the second power rails, the array of the active electronic elements is located in the first direction between the third power rail and the conductor, and each of the active electronic elements is electrically connected to a respective one of the first power rails and a respective one of the second power rails.

27 . The semiconductor device of claim 26 , wherein the active electro

Assignees

• Samsung Electronics Co Ltd

Inventors

• Byun Sung Su

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title