Systems and methods for PLL gain calibration and duty cycle calibration using shared phase detector

Patent metadata

Field	Value
Publication number	US-12119830-B2
Application number	US-202318120819-A
Country	US
Kind code	B2
Filing date	Mar 13, 2023
Priority date	Mar 13, 2023
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

First claim

What is claimed is:

1. A transceiver, comprising:
receive circuitry;
transmit circuitry; and
a phase-locked loop (PLL), the PLL comprising:
a phase detector coupled to a delay element and feedback circuitry,
duty cycle calibration circuitry coupled to an output of the phase detector, and
gain calibration circuitry coupled to the output of the phase detector and an input of gain circuitry.

2. The transceiver of claim 1 , comprising frequency doubling circuitry coupled to an output of the duty cycle calibration circuitry.

3. The transceiver of claim 2 , comprising an additional phase detector coupled to an output of the frequency doubling circuitry, the additional phase detector configured to receive a reference signal and a feedback signal from the feedback circuitry.

4. The transceiver of claim 3 , wherein the additional phase detector is configured to determine a first time offset between the reference signal and the feedback signal.

5. The transceiver of claim 4 , wherein the gain calibration circuitry is configured to adjust loop gain parameters of the gain circuitry based on the first time offset being equal to a second time offset associated with the delay element.

6. The transceiver of claim 4 , wherein the gain calibration circuitry is configured to maintain loop gain parameters of the gain circuitry based on the first time offset being unequal to a second time offset associated with the delay element.

7. The transceiver of claim 1 , wherein the duty cycle calibration circuitry comprises analog duty cycle calibration circuitry and the gain calibration circuitry comprises analog gain calibration circuitry.

8. A phase-locked loop (PLL), comprising:
a phase detector configured to
receive a delayed reference signal,
receive a feedback signal, and
output an error signal based on a first plurality of pulses of the delayed reference signal aligning with a second plurality of pulses of the feedback signal,
gain calibration circuitry configured to
receive the error signal,
output an average value of the error signal, and
adjust loop gain parameters or maintain the loop gain parameters of the PLL based on the average value of the error signal, and
duty cycle calibration circuitry configured to
receive the error signal,
output the average value of the error signal, and
output a duty cycle correction based on the average value of the error signal comprising a positive value or a negative value.

9. The PLL of claim 8 , comprising a delay element configured to apply a time offset to generate the delayed reference signal.

10. The PLL of claim 8 , wherein the gain calibration circuitry is configured to adjust the loop gain parameters of the PLL based on the average value of the error signal indicating that the first plurality of pulses of the delayed reference signal does not align with the second plurality of pulses of the feedback signal.

11. The PLL of claim 8 , wherein the gain calibration circuitry is configured to maintain the loop gain parameters of the PLL based on the average value of the error signal indicating that the first plurality of pulses of the delayed reference signal aligns with the second plurality of pulses of the feedback signal.

12. The PLL of claim 8 , comprising a phase frequency detector configured to determine a time offset based on a reference signal and the feedback signal.

13. The PLL of claim 8 , wherein the phase detector comprises an Alexander phase detector.

14. A method, comprising:
receiving a reference signal at a time-to-digital converter (TDC) of a phase-locked loop (PLL);
receiving a feedback signal at the TDC from feedback circuitry; and
outputting, via the TDC, an error signal to gain calibration circuitry and duty cycle calibration circuitry based on whether a first plurality of pulses associated with the reference signal are aligned with a second plurality of pulses associated with the feedback signal.

15. The method of claim 14 , comprising determining, via the gain calibration circuitry, whether the reference signal and the feedback signal are in-phase based on an indication that the first plurality of pulses and the second plurality of pulses are aligned.

16. The method of claim 15 , comprising maintaining, via the gain calibration circuitry, loop gain parameters of gain circuitry of the PLL based on determining that the reference signal and the feedback signal are in-phase.

17. The method of claim 14 , comprising determining, via the gain calibration circuitry, whether the reference signal and the feedback signal are out of phase based on an indication that the first plurality of pulses and the second plurality of pulses are unaligned.

18. The method of claim 17 , comprising adjusting, via the gain calibration circuitry, loop gain parameters of gain circuitry of the PLL based on determining that the reference signal and the feedback signal are out of phase.

19. The method of claim 14 , comprising adjusting, via the duty cycle calibration circuitry, a duty cycle of the reference signal based on an average direct current (DC) value of the error signal comprising a nonzero value.

20. The method of claim 19 , comprising determining, via the duty cycle calibration circuitry, the average DC value of the error signal comprises the nonzero value.

Assignees

• Apple Inc

Inventors

• Park Jongmin
• Megawer Karim M
• Mayer Thomas

Classifications

• H03L7/0818

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title

• H03L7/195

  in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency (H03L7/193 takes precedence) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title