Matrix phase interpolator for phase locked loop

Patent metadata

Field	Value
Publication number	US-11245402-B2
Application number	US-202117327512-A
Country	US
Kind code	B2
Filing date	May 21, 2021
Priority date	Sep 16, 2016
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

First claim

I claim:

1. A method comprising:
obtaining a plurality of phases of a reference clock signal and a plurality of phases of a local oscillator signal;
generating, using at least two sets of comparators, at least two sets of phase-error signals, each respective set of phase-error signals being associated with a fixed phase offset and wherein each set of phase-error signals comprises comparisons of the plurality of phases of the reference clock signal to corresponding phases of the local oscillator signal having the fixed phase offset;
selecting sets of phase-error signals having adjacent fixed phase offsets;
applying respective weighting factors to each of the selected sets of phase-error signals, the respective weighting factors associated with an intermediate phase in between the adjacent fixed phase offsets of the selected sets of phase-error signals;
generating, using a summation circuit, a composite phase-error signal by forming a summation of the selected sets of phase-error signals; and
providing the composite phase-error signal to a local oscillator generating the plurality of phases of the local oscillator signal.

2. The method of claim 1 , wherein each comparator in the at least two sets of comparators is a dynamically-weighted exclusive OR (XOR) phase comparator receiving a phase of the reference clock signal and the corresponding phase of the local oscillator signal.

3. The method of claim 2 , wherein applying the respective weighting factor to a given phase-error signal comprises generating a plurality of weighted segments, each weighted segment generated by enabling a corresponding logic branch of the dynamically-weighted XOR phase comparator responsive of a respective input logic combination of a given phase of the reference clock signal and the corresponding phase of the local oscillator signal.

4. The method of claim 1 , wherein the comparisons of the plurality of phases of the reference clock signal to the corresponding phases of the local oscillator signal having the fixed phase offset for each set of phase-error signals are logical exclusive OR (XOR) comparisons.

5. The method of claim 1 , further comprising obtaining a respective set of control bits for each selected set of phase-error signals, the control bits indicative of the respective weighting factor.

6. The method of claim 5 , wherein each respective set of control bits comprises N b bits, and wherein the intermediate phase is controlled with a resolution of N b +1 bits, wherein N is an integer greater than 1.

7. The method of claim 1 , wherein the respective weighting factors comprise weighting factors a and b, wherein a+b=c, wherein a and b are integers greater than 0 and wherein c is an integer greater than 2.

8. The method of claim 1 , wherein the weighting factor for each phase-error signal in a given selected set of phase-error signals is equal.

9. The method of claim 1 , wherein the adjacent fixed phase offsets have a difference of 45 degrees.

10. The method of claim 1 , wherein the adjacent fixed phase offsets have a difference of 90 degrees.

11. An apparatus comprising:
a matrix phase comparator configured to obtain a plurality of phases of a reference clock signal and a plurality of phases of a local oscillator signal, the matrix phase comparator configured to:
generate, using at least two sets of comparators, at least two sets of phase-error signals, each respective set of phase-error signals being associated with a fixed phase offset and wherein each set of phase-error signals comprises comparisons of the plurality of phases of the reference clock signal to corresponding phases of the local oscillator signal having the fixed phase offset;
select sets of phase-error signals having adjacent fixed phase offsets; and
apply respective weighting factors to each of the selected sets of phase-error signals, the respective weighting factors associated with an intermediate phase in between the adjacent fixed phase offsets of the selected sets of phase-error signals; and

a summation circuit configured to generate a composite phase-error signal by forming a summation of the selected sets of phase-error signals, and to provide the composite phase-error signal to a local oscillator generating the plurality of phases of the local oscillator signal.

12. The apparatus of claim 11 , wherein each comparator in the at least two sets of comparators is a dynamically-weighted exclusive OR (XOR) phase comparator receiving a phase of the reference clock signal and the corresponding phase of the local oscillator signal.

13. The apparatus of claim 12 , wherein the matrix phase comparator is configured to apply the respective weighting factor to a given phase-error signal by generating a plurality of weighted segments, each weighted segment generated by enabling a corresponding logic branch of the dynamically-weighted XOR phase comparator responsive of a respective input logic combination of a given phase of the reference clock signal and the corresponding phase of the local oscillator signal.

14. The apparatus of claim 11 , wherein each comparator of the at least two sets of comparators is a logical exclusive OR (XOR) comparator.

15. The apparatus of claim 11 , wherein the matrix phase comparator is further configured to obtain a respective set of control bits for each selected set of phase-error signals, the control bits indicative of the respective weighting factor.

16. The apparatus of claim 15 , wherein each respective set of control bits comprises N b bits, and wherein the intermediate phase is controlled with a resolution of N b +1 bits, wherein N is an integer greater than 1.

17. The apparatus of claim 11 , wherein the respective weighting factors comprise weighting factors a and b, wherein a+b=c, wherein a and b are integers greater than 0 and wherein c is an integer greater than 2.

18. The apparatus of claim 11 , wherein the weighting factor for each phase-error signal in a given selected set of phase-error signals is equal.

19. The apparatus of claim 11 , wherein the adjacent fixed phase offsets have a difference of 45 degrees.

20. The apparatus of claim 11 , wherein the adjacent fixed phase offsets have a difference of 90 degrees.

Assignees

• Kandou Labs SA

Inventors

• Tajalli Armin

Classifications

• H03L7/0998 Primary

  using phase interpolation · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title