PLL with wide frequency coverage

Patent metadata

Field	Value
Publication number	US-10778236-B2
Application number	US-201916240702-A
Country	US
Kind code	B2
Filing date	Jan 4, 2019
Priority date	Jan 4, 2019
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.

First claim

What is claimed is:

1. An extended-range PLL comprising:
a feedback divider that produces a feedback clock;
a phase comparator that determines a phase error between a reference clock and the feedback clock;
a loop filter that converts the phase error into a control signal;
a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal;
a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and
a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal,
the divide-by-1.5 block including:
a first divider that produces a first clock signal having a first phase and a first frequency that is one third of the generated clock frequency;
a second divider that produces a second clock signal having the first frequency and a second phase that is 180° apart from the first phase;
a combiner that combines the first clock signal with the second clock signal to obtain a combined clock signal having a second frequency that is twice the first frequency; and
a duty cycle correction circuit that derives the reduced-frequency clock signal from the combined clock signal, the duty-cycle correction circuit having a digital calibration section with:
a delay element that accepts an input clock and produces a delayed clock with a digitally-controlled delay; and
a combining block that combines the input clock with the delayed clock to produce a calibrated clock having a duty cycle closer to 50% than the duty cycle of the input clock.

2. The extended-range PLL of claim 1 , wherein the combining block includes an OR gate.

3. The extended-range PLL of claim 1 , wherein the duty-cycle correction circuit includes an analog calibration section with:
a correction amplifier that produces the reduced-frequency clock signal in response to the calibrated clock; and
a feedback amplifier that adjusts an effective threshold for the correction amplifier to adjust a duty cycle of the reduced-frequency clock signal towards 50%.

4. The extended-range PLL of claim 3 , wherein the digital calibration section and the analog calibration section both are utilized and are in series.

5. The extended-range PLL of claim 4 , wherein the duty cycle correction circuit further comprises a controller that adjusts the digitally-controlled delay when the analog calibration section is unable to fully adjust the duty cycle of the reduced frequency clock signal to 50%.

6. The extended-range PLL of claim 1 , wherein the feedback divider derives the feedback clock directly from the generated clock signal.

7. An extended-range PLL comprising:
a feedback divider that produces a feedback clock;
a phase comparator that determines a phase error between a reference clock and the feedback clock;
a loop filter that converts the phase error into a control signal;
a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal;
a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and
a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal,
wherein the feedback divider produces the feedback clock in response to the selected clock signal.

8. The extended-range PLL of claim 7 , further comprising:
a post-divider that converts the generated clock signal into an output clock signal having an output clock frequency that is 1/M of a frequency of the selected clock signal, M being a selectable positive integer.

9. The extended-range PLL of claim 8 , wherein selectable values of M consist only of powers of two.

10. A clock generation method comprising:
determining a phase error between a reference clock and a feedback clock;
filtering the phase error to yield a control signal;
using a voltage-controlled oscillator (VCO) to provide a generated clock signal having a generated clock frequency determined by the control signal;
deriving a reduced-frequency clock signal from the generated clock signal with a divide-by-1.5 block;
multiplexing a selected one of the generated clock signal and the reduced-frequency clock signal onto a selected clock signal line; and
producing the feedback clock by dividing down a frequency of the selected one of the generated clock signal and the reduced-frequency clock signal.

11. The clock generation method of claim 10 , wherein said deriving includes:
producing a first clock signal having a first phase and a first frequency that is one third of the generated clock frequency;
producing a second clock signal having the first frequency and a second phase that is 180° apart from the first phase; and
combining the first clock signal with the second clock signal to obtain a combined clock signal having a second frequency that is twice the first frequency.

12. The clock generation method of claim 11 , wherein said deriving further includes adjusting the combined clock signal to have a 50% duty cycle.

13. The clock generation method of claim 12 , wherein said adjusting includes at least one of:
performing a digital calibration on the combined clock signal to produce a coarsely-calibrated clock; and
performing an analog calibration on the coarsely-calibrated clock to achieve a 50% duty cycle in the reduced-frequency clock signal.

14. The clock generation method of claim 13 , wherein said adjusting further includes:
modifying the digital calibration when the analog calibration is unable to fully achieve the 50% duty cycle.

15. A divide-by-1.5 circuit that comprises:
a first divider that produces a first clock signal having a first phase and a first frequency that is one third of an input clock frequency;
a second divider that produces a second clock signal having the first frequency and a second phase that is 180° apart from the first phase; and
a combiner that combines the first clock signal with the second clock signal to obtain a combined clock signal having a second frequency that is twice the first frequency; and
a duty cycle correction circuit that derives the reduced-frequency clock signal from the combined clock signal, the duty-cycle correction circuit having a digital calibration section with:
a delay element that accepts the combined clock signal and produces a delayed clock signal with a digitally-controlled delay; and
a combining block that combines the combined clock signal with the delayed clock signal to produce a calibrated clock signal having a duty cycle closer to 50% than the duty cycle of the combined clock signal.

16. The divide-by-1.5 circuit of claim 15 , wherein the duty-cycle correction circuit includes an analog calibration section with:
a correction amplifier that produces the reduced-frequency clock signal in response to the calibrated clock signal; and
a feedback amplifier that adjusts an effective threshold for the correction amplifier to adjust a duty cycle of the reduced-frequency clock signal towards 50%.

17. The divide-by-1.5 circuit of claim 16 , wherein the duty cycle correction circuit further comprises a controller that adjusts the digitally-controlled delay when the analog calibration section is unable to fully adjust the duty cycle of the reduced frequency clock signal to 50%.

18. The divide-by-1.5 circuit of claim 16 , wherein the digital calibration section and the analog calibration section are in series.

Assignees

• Credo Tech Group Ltd

Inventors

• Aga Arshan
• Gao Xiang
• Xu Ni

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0998 Primary

  using phase interpolation · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K21/10

  comprising logic circuits · CPC title