Efficient duty-cycle balanced clock generation circuit for single and multiple-phase clock signals

Patent metadata

Field	Value
Publication number	US-9742386-B2
Application number	US-201514969641-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Dec 15, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed.

First claim

What is claimed is:

1. A circuit comprising:
a first pulse generator configured to generate a first pulse responsive to a rising edge of a first clock signal;
a second pulse generator configured to generate a second pulse responsive to a rising edge of a second clock signal, wherein the second clock signal has a phase opposite that of the first clock signal, wherein the first clock signal is an input clock signal, and wherein the circuit further includes a plurality of delay elements, wherein at least a first subset of the plurality of delay elements is coupled between an input to the first pulse generator and an input to the second pulse generator and is configured to provide a total delay of one half of one cycle of the first clock signal in order to produce the second clock signal;
a clock generation circuit configured to generate an output clock signal by setting an output clock node to a first state responsive to generation of the first pulse and setting the output clock node to a second state responsive to generation of the second pulse; wherein the clock generation circuit includes:
first and second cross-coupled inverters, wherein an output of the first inverter and an input of the second inverter are each coupled to the output node;
a pull-up circuit configured to pull the output node high responsive to receiving the first pulse; and
a pull-down circuit configured to pull the output node low responsive to receiving the second pulse;

wherein the circuit further comprises a second subset of the plurality of delay elements coupled between the input to the second pulse generator and a phase detector and configured to produce a third clock signal that is a version of the first clock signal delayed by a full cycle, wherein the phase detector is coupled to receive the first and third clock signals and configured to adjust a delay provided by each of the plurality of delay elements based on any phase difference between the first and third clock signals.

2. The circuit as recited in claim 1 , wherein the first and second pulse generators are configured to produce respective pulses having pulse widths less than a duty cycle of the input clock signal.

3. An apparatus comprising:
a plurality of pulse generation circuits;
a plurality of clock generation circuits, wherein each of the clock generation circuits includes:
a first input coupled to receive a respective first pulse from one of the plurality of pulse generation circuits, wherein each of the clock generation circuits includes a pull-up circuit configured to cause a corresponding output node to be pulled high responsive to receiving its respective first pulse; and
a second input coupled to receive a respective second pulse from another one of the plurality of clock generation circuits, wherein each of the pulse generation circuits include a pull-down circuit configured to cause the corresponding output node to be pulled low responsive to receiving its respective second pulse;

a plurality of serially-coupled delay elements, wherein a first one of the plurality of serially-coupled is coupled to receive an input clock signal, and wherein an output of each of the serially coupled delay elements is coupled to a corresponding one of the plurality of pulse generation circuits, and wherein at least a subset of the plurality of serially-coupled delay elements is configured to provide an adjustable amount of delay; and
a phase detector coupled to receive first and second delayed versions of the input clock signal and configured to adjust the delay of each of the subset of delay elements such that each of the plurality of clock generation circuits is configured to provide a respective one of a plurality of output clock signals each having a unique phase relationship to each of the other output clock signals.

4. The apparatus as recited in claim 3 , wherein the plurality of pulse generation circuits is arranged such that the second input of each of the plurality of clock generation circuits receives a pulse from its respectively coupled one of the plurality of pulse generation circuits one half clock cycle after the first input of each of the plurality of clock generation circuits receives a pulse from its respectively coupled one of the plurality of pulse generation circuits.

5. The apparatus as recited in claim 3 , wherein each of the pulse generation circuits include an AND gate having first and second inputs, and a delay circuit, wherein the first input and the delay circuit are coupled to receive a version of the clock signal from a respectively coupled one of the plurality of delay elements, and wherein the second input of each pulse generation circuit is configured to receive an output from its respective delay circuit.

6. The apparatus as recited in claim 3 , wherein each of the plurality of clock generation circuits includes a state element configured to hold the output node high after deactivation of the pull-up circuit and further configured to hold the output node low after deactivation of the pull-down circuit.

7. The apparatus as recited in claim 6 , wherein the state element comprises a pair of cross-coupled inverters.

8. The apparatus as recited in claim 3 , wherein the second delayed version of the clock signal received by the phase detector is delayed by a full clock cycle relative to the first delayed version of the clock signal.

9. The apparatus as recited in claim 3 , wherein the phase detector is configured to:
reduce an amount of delay provided by each of the subset of the plurality of delay elements responsive to receiving a rising edge of the first delayed version of the clock signal prior to receiving a rising edge of the second delayed version of the clock signal; and
increase an amount of delay provided by each of the subset of the plurality of delay elements responsive to receiving the rising edge of the first delayed version of the clock signal subsequent to receiving the rising edge of the second delayed version of the input clock signal.

10. The apparatus as recited in claim 3 , wherein the subset of the plurality of delay elements are arranged to divide the first delayed version of the clock signal into 2n delay segments, wherein n is an integer value, and wherein an output of a 2n th delay element is the second delayed version of the input clock signal.

11. The apparatus as recited in claim 3 , wherein each of the subset of the plurality of delay elements is configured to provide an amount of delay that is substantially equal to an amount of delay provided by each of the other ones of the subset of the plurality of delay elements.

12. The apparatus as recited in claim 3 , wherein the phase detector is configured to cause the amount of delay to be adjusted by a substantially equal amount for each of the subset of the plurality of delay elements.

13. A method comprising:
providing a first clock signal to a first one of a plurality of serially-coupled delay elements and a first one of a plurality of pulse generation circuits;
providing, to a first input of each of a plurality of clock generation circuits, a respective first pulse from a first correspondingly coupled one of the pulse generation circuits, wherein each of the pulse generation circuits is coupled to an output of a corresponding one of the plurality of delay elements such that each clock generation circuit receives its respective first pulse at different times with respect to one another;
providing, to a second input of each of the plurality of clock generation circuits, a respective second pulse from a second correspondingly coupled one of the pulse generation circuits, wherein the plurality of delay elements and p

Assignees

• Apple Inc

Inventors

• Jin Haiming

Classifications

• H03K5/15 Primary

  Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors (distributing, switching or gating arrangements H03K17/00) · CPC title

• H03K5/1504 Primary

  using a chain of active delay devices (H03K5/15053 takes precedence) · CPC title