Digital phase-locked loop and method of operating the same

Patent metadata

Field	Value
Publication number	US-9564908-B2
Application number	US-201514955802-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Dec 3, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.

First claim

What is claimed is:

1. A digital phase-locked loop (DPLL) comprising:
a first tracking unit configured to receive a reference signal and a feedback signal generated by feeding back an output signal of the DPLL and output a delayed reference signal by tracking the feedback signal; and
a second tracking unit configured to receive the delayed reference signal and a delayed feedback signal generated by delaying the feedback signal, and generate the output signal of the DPLL, the second tracking unit configured to control a frequency of the output signal of the DPLL according to a phase difference between the delayed feedback signal and the delayed reference signal.

2. The DPLL of claim 1 , wherein the first tracking unit comprises:
a first bangbang phase detector (BBPD) configured to detect a phase difference between the reference signal and the feedback signal, and output a first detection signal based on the phase difference detected by the first BBPD; and
a first delay-controlled delay line (DCDL) configured to generate the delayed reference signal by delaying the reference signal, based on the phase difference detected by the first BBPD.

3. The DPLL of claim 2 , wherein the first tracking unit further comprises:
an accumulation circuit configured to,
receive the first detection signal from the first BBPD,
generate a control signal to delay the reference signal, and
transmit the control signal to the first DCDL in response to the first detection signal.

4. The DPLL of claim 1 , wherein the second tracking unit comprises:
a second BBPD configured to detect a phase difference between the delayed feedback signal and the delayed reference signal, and output a second detection signal based on the phase difference detected by the second BBPD; and
a digitally controlled oscillator (DCO) configured to generate the output signal such that the frequency of the output signal is based on the phase difference detected by the second BBPD.

5. The DPLL of claim 4 , wherein the second tracking unit further comprises:
a second DCDL configured to generate the delayed feedback signal by delaying the feedback signal.

6. The DPLL of claim 4 , wherein the second tracking unit further comprises:
a digital loop filter (DLF) configured to,
receive the second detection signal from the second BBPD, and
provide a control signal to the DCO to control the frequency of the output signal generated thereby, the control signal varying in response to the second detection signal.

7. The DPLL of claim 1 , further comprising:
a main divider configured to generate the feedback signal by dividing the output signal.

8. The DPLL of claim 1 , further comprising:
a lock detector configured to detect whether the DPLL is in a lock state, and generate a lock detection signal indicating whether the DPLL is in the lock state; and
an automatic frequency control (AFC) circuit configured to control the frequency of the output signal based on a phase difference between the reference signal and the feedback signal.

9. The DPLL of claim 8 , wherein
the lock detector is configured to provide the lock detection signal to the first tracking unit, and
the first tracking unit is configured to perform a tracking operation when the lock detection signal indicates that the DPLL is in the lock state.

10. The DPLL of claim 8 , wherein
the first tracking unit is configured to output the delayed reference signal such that,
the delayed reference signal has a constant delay amount with respect to the reference signal, when the DPLL is in an unlock state, and
the delayed reference signal has a variable delay amount with respect to the reference signal based on a tracking result, when the DPLL is in a lock state.

11. A digital phase-locked loop (DPLL) comprising:
a feed-forward delay-locked part (FFDLP) configured to receive a reference signal and a feedback signal generated by feeding back an output signal of the DPLL, and output a delayed reference signal by tracking the feedback signal, when the DPLL is in a lock state; and
a phase-locked part (PLP) configured to receive the delayed reference signal and a delayed feedback signal generated by delaying the feedback signal, and generate the output signal of the DPLL.

12. The DPLL of claim 11 , wherein the FFDLP is configured to generate the delayed reference signal by controlling a delay amount for the reference signal according to a phase difference between the reference signal and the feedback signal.

13. The DPLL of claim 11 , wherein the PLP is configured to control a frequency of the output signal of the DPLL according to a phase difference between the delayed feedback signal and the delayed reference signal.

14. The DPLL of claim 13 , wherein the PLP receives the delayed reference signal generated by tracking the feedback signal and the delayed feedback signal generated by delaying the feedback signal, and generates the output signal,
wherein the PLP reduces phase noise of the output signal due to a reduced input tracking jitter.

15. The DPLL of claim 11 , further comprising:
a lock detector configured to detect whether the DPLL is in a lock state based on a phase difference between the delayed feedback signal and the delayed reference signal.

16. A Digital Phase-Locked Loop (DPLL) configured to lock a frequency of a digitally controlled oscillator to a frequency of a feedback signal, the DPLL comprising:
a first circuit configured to receive a reference signal and the feedback signal, and to output a delayed reference signal such that the delayed reference signal is a delayed version of the reference signal that tracks jitters in the feedback signal; and
a second circuit configured to,
receive the delayed reference signal and a delayed feedback signal, the delayed feedback signal being a delayed version of the feedback signal, and
generate an output signal based on the delayed reference signal and the delayed feedback signal such that phase noise in the output signal is reduced due to the delayed reference signal tracking the jitters in the feedback signal.

17. The DPLL of claim 16 , wherein the second circuit comprises:
the digitally controlled oscillator (DCO) configured to control a frequency of the output signal based on a phase difference between the delayed feedback signal and the delayed reference signal.

18. The DPLL of claim 17 , wherein the second circuit further comprises:
a bangbang phase detector (BBPD) configured to detect the phase difference between the delayed feedback signal and the delayed reference signal, and output a detection signal based thereon, and
the DCO is configured to control the frequency of the output signal based on the detection signal.

19. The DPLL of claim 18 , wherein the DPPL further comprising:
a lock detector configured to detect whether the DPLL is in a lock state or an unlock state based on a difference between a frequency of the feedback signal and a frequency of the reference signal, and wherein
the first circuit includes a delay circuit configured to generate the delayed reference signal by delaying the reference signal a constant amount if the DPLL is in the unlock state, and delaying the reference signal a variable amount based on the jitter, if the DPLL is in the lock state.

20. The DPLL of claim 19 , wherein the delay circuit comprises:
a plurality of buffers each configured to delay the reference signal by a unit.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Min-Young
• Kim Tae-Ik
• Kim Ji-Hyun

Classifications

• H03L7/0802

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/081 Primary

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title