Frequency synthesiser

Patent metadata

Field	Value
Publication number	US-9240772-B2
Application number	US-201013262626-A
Country	US
Kind code	B2
Filing date	Mar 30, 2010
Priority date	Apr 3, 2009
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A low power frequency synthesizer circuit for a radio transceiver, the synthesizer circuit comprising:
a digital controlled oscillator configured to generate an output signal (F o ) having a frequency controlled by an input digital control word (DCW); a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

First claim

The invention claimed is:

1. A low power frequency synthesiser circuit, comprising:
a digital controlled oscillator configured to generate an output signal having a frequency controlled by an input digital control word;
a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word and the output signal; and
a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal;
wherein the feedback loop comprises a first feedback loop configured to provide a first part of the digital control word for coarse control of the frequency of the output signal of the digital controlled oscillator and a second feedback loop configured to provide a second part of the digital control word for fine control of the frequency of the output signal of the digital controlled oscillator; and

wherein
the first feedback loop includes
a counter module configured and arranged to count a number of clock cycles in the output signal of the digital controlled oscillator in each clock cycle of the input reference clock signal, and
a first subtractor configured and arranged to generate the first part of the digital control word based on a difference between the number of clock cycles indicated by the counter and a first part of the frequency control word; and

the second feedback loop includes
the counter module, and

a second subtractor configured and arranged to generate the second part of the digital control word based on a difference between the number of clock cycles indicated by the counter and a second part of the frequency control word.

2. The frequency synthesiser circuit of claim 1 , wherein:
the duty cycle module is configured to, for each set of a plurality of consecutive sets of M clock cycles of the input reference clock signal, enable the digital controlled oscillator for a first N consecutive clock cycles of the M clock cycles of the set and disable the digital controlled oscillator for the last P clock cycles of the M clock cycles of the set, where P=M−N; and
the feedback loop is configured to store the digital control word in response to one of the plurality of control signals and to use the stored digital control word in controlling the digital controlled oscillator when the digital controlled oscillator is subsequently enabled.

3. The frequency synthesiser circuit of claim 1 , wherein the duty cycle module comprises a finite state machine configured to generate the plurality of control signals driven by the reference clock signal, and the set fraction of clock cycles is based on a duty-cycle of the digital controlled oscillator.

4. The frequency synthesiser circuit of claim 2 , wherein the duty cycle module is configured to provide a control signal to enable the digital controlled oscillator in a preset phase using the stored digital control word for one or more reference clock cycles prior to enabling the output signal from the synthesiser.

5. The frequency synthesiser circuit of claim 1 , wherein the duty cycle module is configured to modulate a temporal position of successive pulses generated by the digital controlled oscillator according to an input data signal.

6. The frequency synthesiser circuit of claim 1 , wherein the feedback loop comprises a counter module and a phase difference module, the counter module being configured to count cycles of the output signal from the digital controlled oscillator while the digital controlled oscillator is enabled and to provide a output phase signal to the phase difference module, the phase difference module configured to receive the input frequency control word and the output phase signal and to provide an error signal output to determine the digital control word.

7. The frequency synthesiser circuit of claim 6 , wherein the duty cycle module is configured to reset the counter when enabling the digital controlled oscillator with one of the plurality of control signals.

8. The frequency synthesiser circuit of claim 1 , wherein: the first feedback loop is configured to control a number of cycles of the output signal of the digital controlled oscillator between successive transitions of the reference clock signal, and the second feedback loop is configured to minimize a time difference between transitions of the output signal of the digital controlled oscillator and corresponding transitions in the reference clock signal.

9. The frequency synthesiser circuit of claim 1 , wherein the first and second feedback loops comprise an accumulator module configured to provide respective parts of the digital control word and to store the parts of the digital control word when the digital controlled oscillator is disabled.

10. The frequency synthesiser circuit of claim 9 , wherein the first feedback loop is configured to alter a more significant respective part of the digital control word only when a number of cycles of the output signal between successive reference clock signal transitions differs from the number of cycles indicated by the frequency control word by one or more cycle.

11. The frequency synthesiser circuit of claim 10 , wherein the second feedback loop is configured to alter a less significant respective part of the digital control word by one or more bits to minimize a time difference between transitions of the output signal and corresponding transitions in the reference clock signal.

12. An integrated circuit comprising the frequency synthesiser of claim 1 .

13. The frequency synthesiser circuit of claim 1 , wherein the periodic enabling and disabling of the digital controlled oscillator, by the duty cycle module, for the set fraction of clock cycles of the input reference clock signal includes periodically alternating between:
enabling the digital controlled oscillator for a first number of the clock cycles; and
disabling the digital controlled oscillator for a second number of the clock cycles.

14. The frequency synthesiser circuit of claim 13 , wherein the disabling of the digital controlled oscillator includes disabling one or more circuits included in the feedback loop.

15. The frequency synthesiser circuit of claim 1 , wherein the error derived from an input frequency control word and the output signal indicates a phase difference between a reference phase and the output signal.

16. The frequency synthesiser circuit of claim 15 , further comprising:
an accumulation circuit configured and arranged to accumulate the input frequency control word to produce the reference phase.

17. The frequency synthesiser circuit of claim 1 , wherein
the first feedback loop exhibits a transfer function, in which the first part of the digital control word generated by the first subtractor is null when the number of clock cycles indicated by the counter is equal to the first part of the frequency control word.

Assignees

• Drago Salvatore
• Sebastiano Fabio
• Leenaerts Dominicus Martinus Wilhelmus
• Breems Lucien Johannes
• Nauta Bram
• Nxp Bv

Inventors

• Drago Salvatore
• Sebastiano Fabio
• Leenaerts Dominicus Martinus Wilhelmus
• Breems Lucien Johannes
• Nauta Bram

Classifications

• H03L7/107

  using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth · CPC title

• H03L7/103

  the additional signal being a digital signal · CPC title

• H03L7/0802

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title