Electronic circuit having serial latch scan chains

Patent metadata

Field	Value
Publication number	US-10459031-B2
Application number	US-201414520115-A
Country	US
Kind code	B2
Filing date	Oct 21, 2014
Priority date	Oct 21, 2013
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

The invention relates to an electronic circuit (10) having one or more latch scan chains (12), the electronic circuit (10) comprising (i) a built-in test structure (14); (ii) generation means (16) for simultaneously generating scan-in data for each of said scan chains (12); (iii) interception means (18) for simultaneously intercepting test lines (20) of said scan chains (12), said test lines (20) comprising scan-in lines (22) and/or control lines (24). Said interception means (18) are responsive to said generation means (16) in order to simultaneously feed the generated scan-in data into each of said scan chains (12) for initializing the electronic circuit (10). The invention further relates to a method for initializing an electronic circuit (10), as well as a data processing system (210) for initializing an electronic circuit (10).

First claim

The invention claimed is:

1. An electronic circuit coupled to one or more latch scan chains, the electronic circuit comprising:
a logic built in self test (LBIST) including a test control register initialized to generate scan-in data, the scan-in data comprising a pre-determined initialization pattern;
an interception circuit provided outside of the LBIST and connected to the LBIST through a multiplexer, the interception circuit configured to apply a control signal to the LBIST through the multiplexer during a power on process or an exit of a deep power management state of the electronic circuit, the control signal configured to cause the test control register to generate the scan-in data including the pre-determined initialization pattern and provide the pre-determined initialization pattern to the one or more latch scan chains in parallel to initialize the electronic circuit during the power on process or exit of the deep power management state.

2. The electronic circuit according to claim 1 , wherein the interception circuit is further configured to:
determine whether the pre-determined initialization pattern is to be used for an additional initialization cycle; and
in response to determining that the pre-determined initialization pattern is to be used for an additional initialization cycle, apply the control signal to the first LBIST through the multiplexer for the additional initialization cycle.

3. The electronic circuit according to claim 2 , wherein the interception circuit is further configured to:
in response to determining that the pre-determined initialization pattern is not to be used for an additional initialization cycle, perform one of:
apply a second control signal to the first LBIST through the multiplexer, the second control signal configured to cause a second test control register to generate second scan-in data including a second pre-determined initialization pattern and provide the second pre-determined initialization pattern simultaneously to the one or more latch scan chains in parallel to initialize the electronic circuit and;
reinitialize the test control register to a value other than the scan-in data.

4. The electronic circuit according to claim 1 , wherein the interception circuit comprises a state machine.

5. The electronic circuit according to claim 1 , further comprising:
wherein the LBIST is connected to input lines of the one or more latch scan chains, and output lines of the one or more latch scan chains are connected back to the LBIST.

6. The electronic circuit according to claim 1 , further comprising:
a second LBIST connected to the LBIST and to one or more of the latch scan chains;
wherein the test control register of the LBIST is configured to provide the pre-determined initialization pattern to the second LBIST, the second LBIST providing the pre-determining initialization pattern to the one or more latch scan chains connected to the second LBIST in parallel to initialize the electronic circuit during the power on process or exit of the deep power management state.

7. A method for initializing an electronic circuit including a logic built in self test (LBIST) and an interception circuit provided outside of a first LBIST and connected to the first LBIST through a multiplexer, wherein the electronic circuit is coupled to one or more latch scan chains, the method comprising:
initializing a test control register of the LBIST to generate scan-in data, the scan-in data comprising a pre-determined initialization pattern;
applying, by the interception circuit, a control signal to the LBIST through the multiplexer during a power on process or an exit of a deep power management state of the electronic circuit the control signal causing the test control register to generate the scan-in data including the pre-determined initialization pattern and provide the pre-determined initialization pattern to the one or more latch scan chains in parallel to initialize the electronic circuit during the power on process or exit of the deep power management state.

8. The method according to claim 7 , wherein the initialization of the electronic circuit further comprises:
determining whether the pre-determined initialization pattern is to be used for an additional initialization cycle; and
in response to determining that the pre-determined initialization pattern is to be used for an additional initialization cycle, applying, by the interception circuit, the control signal to the first LBIST through the multiplexer for the additional initialization cycle.

9. The method according to claim 7 , wherein the initialization of the electronic circuit further comprises:
in response to determining that the pre-determined initialization pattern is not to be used for an additional initialization cycle performing one of:
applying, by the interception circuit, a second control signal to the first LBIST through the multiplexer, the second control signal causing a second test control register to generate second scan-in data including a second pre-determined initialization pattern and provide the second pre-determined initialization pattern simultaneously to the one or more latch scan chains in parallel to initialize the electronic circuit; and
reinitializing the control register to a value other than the scan-in data.

10. The method according to claim 7 , and further comprising implementing the interception circuit utilizing a state machine.

11. The method according to claim 7 , wherein the control signal causes the test control register to provide the pre-determined initialization pattern to a second LBIST connected to the LBIST and to one or more of the latch scan chains, the second LBIST providing the pre-determining initialization pattern to the one or more latch scan chains connected to the second LBIST in parallel to initialize the electronic circuit during the power on process or exit of the deep power management state.

12. A computer program product, comprising:
a non-transitory computer-readable storage device;
program code stored in the computer-readable storage device for initializing an electronic circuit including a first logic built in self test (LBIST) and an interception circuit connected to the LBIST through a multiplexer, wherein the electronic circuit is coupled to one or more latch scan chains, wherein the program code, when executed by a processor, causes the processor to perform:
initializing a test control register of the LBIST to generate scan-in data, the scan-in data comprising a pre-determined initialization pattern;
applying, by the interception circuit, a control signal to the LBIST through the multiplexer during a power on process or an exit of a deep power management state of the electronic circuit the control signal causing the test control register to generate the scan-in data including the pre-determined initialization pattern and provide the pre-determined initialization pattern to the one or more latch scan chains in parallel to initialize the electronic circuit during the power on process or exit of the deep power management state.

13. The program product according to claim 12 , wherein to initialize the electronic circuit, the program code causes the processor to perform:
determining whether the pre-determined initialization pattern is to be used for an additional initialization cycle; and
in response to determining that the pre-determined initialization pattern is to be used for an additional initialization cycle, applying, by the interception circuit, the control signal to the first LBIST through the multiplexer for the additional initialization cycle.

14. The program product

Assignees

• Globalfoundries Inc

Inventors

• Gloekler Tilman
• Koenig Andreas
• Kuenzer Jens
• Lichtenau Cedric

Classifications

• G06F11/27

  Built-in tests · CPC title

• G01R31/318544 Primary

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G06F11/2284 Primary

  by power-on test, e.g. power-on self test [POST] · CPC title

• G01R31/318563 Primary

  Multiple simultaneous testing of subparts · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title