Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits

Patent metadata

Field	Value
Publication number	US-9947419-B1
Application number	US-201715472121-A
Country	US
Kind code	B1
Filing date	Mar 28, 2017
Priority date	Mar 28, 2017
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.

First claim

What is claimed is:

1. An apparatus, comprising:
a first latch configured to:
latch a data signal in response to a first state of a clock signal if a scan shift signal is deasserted; and
latch a test vector signal in response to the first state of the clock signal if the scan shift signal is asserted; and

a second latch configured to:
latch a write mask signal in response to the first state of the clock signal if the scan shift signal is deasserted; and
latch the test vector signal in response to the first state of the clock signal if the scan shift signal is asserted.

2. The apparatus of claim 1 , further comprising a gating circuit configured to:
route the test vector signal from a scan input port to the first and second latches in response to the scan shift signal being asserted; and
prevent the routing of the test vector signal from the scan input port to the first and second latches in response to the scan shift signal being deasserted.

3. The apparatus of claim 2 , wherein the gating circuit comprises:
a first pass gate coupled between the scan input port and the first latch, wherein the first pass gate turns on in response to the scan shift signal being asserted, and turns off in response to the scan shift signal being deasserted; and
a second pass gate coupled between the scan input port and the second latch, wherein the second pass gate turns on in response to the scan shift signal being asserted, and turns off in response to the scan shift signal being deasserted.

4. The apparatus of claim 1 , further comprising a gating device coupled between a data input port for receiving the data signal and an input of the first latch, wherein the gating device is configured to:
generate the data signal at an output of the gating device in response to the scan shift signal being deasserted; and
tristate the output in response to the scan shift signal being asserted.

5. The apparatus of claim 1 , further comprising a gating device coupled between a write mask input port for receiving the write mask signal and an input of the second latch, wherein the gating device is configured to:
generate the write mask signal at an output of the gating device in response to the scan shift signal being deasserted; and
tristate the output in response to the scan shift signal being asserted.

6. The apparatus of claim 1 , wherein the first latch comprises:
a first inverter;
a pass gate configured to:
pass the data signal or the test vector signal from an input of the pass gate to the first inverter in response to a second state of the clock signal;
decouple the input from the first inverter in response to the first state of the clock signal;

a second inverter configured to:
be cross-coupled with the first inverter to latch the data signal or the test vector signal in response to the first state of the clock signal; and
not be cross-coupled with the first inverter in response to the second state of the clock signal.

7. The apparatus of claim 1 , wherein the second latch comprises:
a first inverter; and
a pass gate configured to:
pass the write mask signal or the test vector signal from an input of the pass gate to the first inverter in response to a second state of the clock signal;
decouple the input from the first inverter in response to the first state of the clock signal;

a second inverter configured to:
be cross-coupled with the first inverter to latch the write mask signal or the test vector signal in response to the first state of the clock signal; and
not be cross-coupled with the first inverter in response to the second state of the clock signal.

8. The apparatus of claim 1 , further comprising a third latch configured to latch the test vector signal in response to a second state of the clock signal if the scan shift signal is asserted, wherein the latched test vector signal is produced at a scan output port.

9. The apparatus of claim 1 , wherein the third latch comprises:
a first inverter;
a pass gate configured to:
pass the test vector signal from an input of the pass gate to the first inverter in response to the first state of the clock signal;
decouple the input from the first inverter in response to the second state of the clock signal;

a second inverter configured to:
be cross-coupled with the first inverter to latch the test vector signal in response to the second state of the clock signal; and
not be cross-coupled with the first inverter in response to the first state of the clock signal.

10. The apparatus of claim 1 , further comprising a data write circuit configured to write data to a memory cell coupled to complementary bitlines based on the data signal if the write mask signal is deasserted.

11. The apparatus of claim 10 , wherein the data write circuit comprises:
a first OR-gate or first NOR-gate including a first input configured to receive the latched data signal from the first latch, a second input configured to receive the latched write mask signal from the second latch, and an output coupled to one of the complementary bitlines; and
a second OR-gate or second NOR-gate including a first input configured to receive the data signal from the first latch, a second input configured to receive the latched write mask signal from the second latch, and an output coupled to the other of the complementary bitlines.

12. The apparatus of claim 11 , wherein the data write circuit comprises:
a first pass gate configured to route the data signal from the first OR-gate or the first NOR-gate to the one of the complementary bitlines in response to an asserted state of a bitline select signal; and
a second pass gate configured to route the data signal from the second OR-gate or the second NOR-gate to the other of the complementary bitlines in response to the asserted state of the bitline select signal.

13. The apparatus of claim 11 , further comprising a third latch configured to latch the test vector signal in response to a second state of the clock signal if the scan shift signal is asserted, wherein the latched test vector signal is produced at a scan output port, and wherein the first OR-gate or first NOR-gate is coupled between the first latch and the third latch.

14. A method, comprising:
latching a data signal at a first node in response to a first state of a clock signal if a scan shift signal is deasserted;
latching a test vector signal at the first node in response to the first state of the clock signal if the scan shift signal is asserted;
latching a write mask signal at a second node in response to the first state of the clock signal if the scan shift signal is deasserted; and
latching the test vector signal at the second node in response to the first state of the clock signal if the scan shift signal is asserted.

15. The method of claim 14 , further comprising:
routing the test vector signal from a scan input port to first and second latches for latching the test vector signal at the first and second nodes, respectively, in response to the scan shift signal being asserted; and
decoupling the scan input port from the first and second latches in response to the scan shift signal being deasserted.

16. The method of claim 14 , further comprising:
routing the data signal from a data input port to a latch for latching the data signal at the first node in response to the scan shift signal being deasserted; and
decoupling the data input port from the latch in response to the scan shift signal being asserted.

17. The method of claim 14 , further comprising:
routing the write mask signal from a write mask

Assignees

• Qualcomm Inc

Inventors

• Sinha Rakesh Kumar
• Mathuria Priyankar
• Gupta Sharad Kumar

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C2029/1204

  Bit line control · CPC title

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title

• G11C2029/3202

  Scan chain · CPC title

• G11C29/32

  Serial access; Scan testing · CPC title