System and method for memory scan design-for-test

Patent metadata

Field	Value
Publication number	US-9666302-B1
Application number	US-201514980390-A
Country	US
Kind code	B1
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

An IC includes a memory core logic unit, an output unit, and an input unit. The memory logic unit is coupled to a plurality of bit cells configured to control read and write of data to and from the plurality of bit cells. The input unit is formed on the integrated circuit. The output unit is formed on the integrated circuit. The input unit includes a second plurality of multiplexers for signal selection, at least one lock up latch for storing data and configured to increase a hold time for the data, and at least one shadow latch configured to store a copy of the data stored in the at least one lock up latch. The output unit includes a first plurality of multiplexers for signal selection and at least one high phase pass latch for storing data.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a memory logic unit coupled to a plurality of bit cells configured to control read and write of data to and from the plurality of bit cells;
an input unit formed on the integrated circuit, the input unit comprising:
a first plurality of multiplexers for signal selection; and
a first logic gate having a plurality of inputs coupled to outputs of at least two of the first plurality of multiplexers, and an output coupled to inputs of at least another two of the first plurality of multiplexers;

an output unit formed on the integrated circuit, the output unit comprising:
at least one output multiplexer for signal selection; and
at least one high phase pass latch for storing data, and configured to allow the data to pass through when a clock applied to the at least one high phase pass latch has a high phase, at least one lock up latch for storing data and configured to increase a hold time for the data; and
at least one shadow latch configured to store a copy of the data stored in the at least one lock up latch,
wherein electronic connections are established between the memory logic unit and the output unit, electronic connections are established between the memory logic unit and the input unit, and electronic connections are established between the input unit and the output unit, so as to provide a first signal path through the input unit, the memory logic unit, and the output unit, for performing normal data write operations, and at least one additional signal path through the input unit and the output unit, for performing at least one scan test operation.

2. The circuit of claim 1 , wherein the at least one additional path comprises a shift path.

3. The circuit of claim 1 , wherein the at least one additional path comprises a capture path.

4. The circuit of claim 1 , wherein the first and second plurality of multiplexers are configured to allow selection between the first signal path and the at least one additional signal path.

5. The circuit of claim 4 , wherein the first latch and the second latch are low-phase pass latches, the third latch is a shadow latch, the fourth latch is a lock-up latch, and the fifth latch is a high-phase pass latch.

6. A circuit, comprising:
a first multiplexer having a first input, a second input and an output;
a second multiplexer having a first input, a second input and an output,
wherein the first input of the first multiplexer is connected to the first input of the second multiplexer;
a third multiplexer having a first input, a second input, a third input, an output and a selector, wherein the output of the third multiplexer is connected to the input of a first latch;
a fourth multiplexer having a first input, a second input, a third input, an output and a selector, wherein the output of the fourth multiplexer is connected to the input of a second latch, and the first input of the third multiplexer is connected to the first input of the fourth multiplexer, wherein the selector of the third multiplexer is connected to the selector of the fourth multiplexer and both connected to a first selector signal;
a third latch having an input and an output, wherein the input of the third latch is connected to the output of the second multiplexer;
a fourth latch having an input and an output, wherein the input of the fourth latch is connected to the output of the third latch;
a first logic gate having a first input, a second input and an output, wherein the output of the first logic gate is connected to the first input of the first multiplexer and the first input of the second multiplexer, wherein the output of the first latch is connected to an input of the first logic gate and, and the output of the second latch is connected to the other input of the first logic gate; and
a second logic gate having a first input, a second input and an output, wherein an input of the second logic gate is connected to the output of the second multiplexer and the input of the third latch.

7. The circuit of claim 6 , further comprising:
a first level shifter for voltage shifting, wherein the first input of the third multiplexer and the first input of the fourth multiplexer are connected to a first input through the first level shifter.

8. The circuit of claim 6 , further comprising:
a second level shifter for voltage shifting;
a third level shifter for voltage shifting;
a fifth multiplexer having a first input, a second input and an output, wherein the output of the fifth multiplexer is connected to the third input of the third multiplexer through the second level shifter; and
a sixth multiplexer having a first input, a second input and an output, wherein the output of the sixth multiplexer is connected to the third input of the fourth multiplexer through the third level shifter.

9. The circuit of claim 6 , further comprising:
a third logic gate having an input and an output;
a fourth logic gate having a first input, a second input and an output, wherein the input of the third logic gate is connected to the output of the fourth latch, and the output of the third logic gate is connected to the second input of the fourth logic gate.

10. The circuit of claim 6 , further comprising:
a fifth latch having an input and an output;
a seventh multiplexer having a first input, a second input and an output, wherein the output of the fifth latch is connected to the first input of the seventh multiplexer; and
a fifth logic gate having an input and an output, wherein the output of the seventh multiplexer is connected to the input of the fifth logic gate.

11. The circuit of claim 10 , further comprising:
a sixth logic gate having a first input, a second input and an output;
a seventh logic gate having a first input, a second input and an output;
a ninth logic gate having an input and an output, wherein the input of the ninth logic gate is connected to both the output of the first multiplexer and the first input of the seventh logic gate, the output of the ninth logic gate is connected to the first input of the sixth logic gate, wherein the second input of the sixth logic gate is connected to the output of the second logic gate and the second input of the seventh logic gate.

12. The circuit of claim 11 , further comprising:
a sense amplifier having a first input, a second input and an output, wherein the output of the sixth logic gate is connected to the first input of the sense amplifier, and the output of the seventh logic is connected to the second input of the sense amplifier.

13. The circuit of claim 12 , wherein the output of the sense amplifier is connected to the input of the fifth latch, and the second input of the second logic gate is connected to a control signal.

14. A circuit, comprising:
a first multiplexer having a first input, a second input, a third input, an output and a selector, wherein the output of the first multiplexer is connected to an input of a first latch;
a second multiplexer having a first input, a second input, a third input, an output and a selector, wherein the output of the second multiplexer is connected to an input of a second latch, wherein the selector of the first multiplexer is connected to the selector of the second multiplexer and each selector is controlled by a common selector signal;
a first logic gate having a first input, a second input and an output, wherein the first input is connected to the output of the first latch, and the second input is connected to the output of the second latch;
a third latch having an input and an output, wherein the input of the third latch is connected to the output of the fi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ming-Hung
• Chen Chia-Cheng
• Wu Ching-Wei

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title