Complementary die-to-die interface

Patent metadata

Field	Value
Publication number	US-12112113-B2
Application number	US-202117194003-A
Country	US
Kind code	B2
Filing date	Mar 5, 2021
Priority date	Mar 5, 2021
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

First claim

What is claimed is:

1. A system, comprising:
a first instance of a particular integrated circuit die having a die-to-die interface with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry; and
a second instance of the particular integrated circuit die having the die-to-die interface;
wherein the die-to-die interfaces of the first and second instances of the particular integrated circuit die are coupled such that conductive paths from the transmit and receive pins for the particular bus on the first instance are aligned, respectively, to receive and transmit pins for the particular bus on the second instance without crossing.

2. The system of claim 1 , wherein the particular integrated circuit die includes a plurality of transmitter circuits and a plurality of receiver circuits corresponding to respective ones of a plurality of transmit pins and a plurality of receive pins, and wherein the plurality of transmitter circuits and the plurality of receiver circuits are arranged in a physical layout corresponding to the physical pin layout.

3. The system of claim 1 , wherein the particular integrated circuit die includes a plurality of on-chip routers coupled to a bus circuit that supports communication on-chip and between the first and second instances of the particular integrated circuit die, and wherein the plurality of on-chip routers are coupled to respective portions of the die-to-die interface.

4. The system of claim 3 , wherein the transmit and receive pins of the die-to-die interface are grouped into sets of pins, wherein the sets of pins have a common number of pins, and wherein individual ones of the plurality of on-chip routers are assigned to a respective one or more of the sets of pins.

5. The system of claim 4 , wherein a particular on-chip router of the plurality of on-chip routers includes a particular number of pins, different than the common number, and wherein at least one pin of the respective one or more of the sets of pins assigned to the particular on-chip router are unused.

6. The system of claim 3 , wherein a first on-chip router of the plurality of on-chip routers is coupled to the transmit pin for a given I/O signal;
wherein a second on-chip router of the plurality of on-chip routers is coupled to the receive pin for the given I/O signal; and
wherein the first on-chip router is coupled to the second on-chip router.

7. The system of claim 6 , further comprising an interface wrapper wherein the interface wrapper is configured to:
route the transmit pin to a default pin assignment in the first on-chip router; and
route the receive pin to a non-default pin assignment in the second on-chip router.

8. A method, comprising:
sending, by a first instance of a particular integrated circuit design to a second instance of the particular integrated circuit design, first data via a set of transmit pins of a die-to-die interface; and
receiving, by the first instance of the particular integrated circuit design from the second instance of the particular integrated circuit design, second data via a set of receive pins of the die-to-die interface, wherein the set of transmit pins and the set of receive pins are located in complementary positions relative to an axis of symmetry of the particular integrated circuit design; and
wherein the die-to-die interfaces of the first and second instances of the particular integrated circuit design are coupled such that conductive paths attached to transmit and receive pins on the first instance are attached, respectively, to receive and transmit pins on the second instance without crossing.

9. The method of claim 8 , wherein sending, by the first instance, the first data via the set of transmit pins of the die-to-die interface comprises transmitting a particular set of signals to the second instance via the die-to-die interface using a particular on-chip router.

10. The method of claim 9 , wherein receiving, by the first instance, data via the set of receive pins of the die-to-die interface comprises receiving a different set of signals from the second instance via the die-to-die interface using a different on-chip router.

11. The method of claim 8 , wherein the set of transmit pins includes a first number of pins, and wherein sending, by the first instance, data via the set of transmit pins of the die-to-die interface comprises, sending the data in a plurality of data packets, wherein ones of the plurality of data packets include a second number of bits, and wherein the second number is less than the first number.

12. The method of claim 11 , further comprising sending, at a different point in time, a different plurality of data packets, wherein ones of the different plurality of data packets include the first number of bits.

13. The method of claim 8 , wherein a particular transmit pin of the set of transmit pins and a complementary receive pin of the set of receive pins are located a same distance from the axis of symmetry.

14. The method of claim 8 , wherein sending, by the first instance, the first data via the set of transmit pins of the die-to-die interface comprises routing the set of transmit pins to a first on-chip router using a non-default pin assignment; and
wherein receiving, by the first instance, the second data via the set of receive pins of the die-to-die interface comprises routing the set of receive pins to a second on-chip router using a default pin assignment.

15. An apparatus comprising:
a bus circuit configured to transfer given data among a plurality of functional circuits in a particular integrated circuit; and
a die-to-die interface, included in the particular integrated circuit, coupled to the bus circuit and including a plurality of transmitter circuits coupled to a particular set of transmit pins and a plurality of receiver circuits coupled to a particular set of receive pins;
wherein the particular set of transmit pins is arranged in a particular layout relative to an axis of symmetry of the die-to-die interface;
wherein the particular set of receive pins is arranged in a complementary layout to the particular layout, relative to the axis of symmetry; and
wherein the die-to-die interface is configured to transfer particular data between the bus circuit and a different integrated circuit that includes the die-to-die interface in a manner that is transparent to software executing on the apparatus.

16. The apparatus of claim 15 , further comprising a plurality of on-chip routers configured to transfer the particular data between the bus circuit and the die-to-die interface via a plurality of signals.

17. The apparatus of claim 16 , further comprising an interface wrapper coupled to the plurality of on-chip routers and to the die-to-die interface and configured to:
route, for a first portion of the particular data, the plurality of signals between the on-chip routers and the die-to-die interface using a first pin assignment; and
re-route, for a second portion of the particular data, the plurality of signals between the on- chip routers and the die-to-die interface using a second pin assignment different from the first pin assignment.

18. The apparatus of claim 16 , wherein the die-to-die interface includes a plurality of sets of transmit and receive pins, and wherein power signals and clock signals are controlled independently for at least some sets of transmit and receive pins in the plurality of sets of transmit and receive pins.

19. The apparatus of claim 18 , wher

Assignees

• Apple Inc

Inventors

• Kolor Sergio
• Davidov Dany
• Leshem Nir
• Pilip Mark
• Zimet Lior

Classifications

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F2115/02

  System on chip [SoC] design · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title