Stacked semiconductor device and control method for the same

Patent metadata

Field	Value
Publication number	US-10153006-B2
Application number	US-201615283624-A
Country	US
Kind code	B2
Filing date	Oct 3, 2016
Priority date	Oct 14, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A semiconductor device includes semiconductor chips stacked each other. Each of the semiconductor chips converts second reception data received by second reception terminals arranged in point symmetry on the first face by a conversion method to convert first reception data received by first reception terminals arranged in point symmetry on the first face into a reference data; and generates an identification information of the each semiconductor chip based upon the converted second reception data; and outputs the bit sequence obtained by converting the generated identification information by means of the inverse conversion method of the conversion method.

First claim

What is claimed is:

1. A semiconductor device in which a plurality of semiconductor chips are stacked, the semiconductor device comprising:
first reception terminals of the plurality of the semiconductor chips, each of the first reception terminals being arranged in point symmetry on a first face;
first transmission terminals of the plurality of the semiconductor chips, each of the first transmission terminals being arranged on a second face that is a back face of the first face, and each of the first transmission terminals lying over one of the first reception terminals of the plurality of the semiconductor chips in a plane view; and
second reception terminals of the plurality of the semiconductor chips, each of the second reception terminals being arranged in point symmetry on the first face, and the second reception terminals being different from the first reception terminals of the plurality of the semiconductor chips;
each of the plurality of the semiconductor chips includes second transmission terminals of the plurality of the semiconductor chips, the second transmission terminals being arranged on the second face and lying over the second reception terminals of the plurality of the semiconductor chips in a plane view;
when another semiconductor chip is arranged on the second face, the first transmission terminals of the plurality of the semiconductor chips are connected to the first reception terminals of the another semiconductor chip, and the second transmission terminals of the plurality of the semiconductor chips are connected to the second reception terminals of the another semiconductor chip; and
a second reception data received by the second reception terminals is converted into data based on a first reception data received by the first reception terminals, and reference data, the reference data being fixed data;
an identification information of each of the plurality of the semiconductor chips is generated based on the data; and
a bit sequence based on the identification information is outputted from the second transmission terminals.

2. The semiconductor device according to claim 1 , wherein
the plurality of the semiconductor chips are two in number, and
each of the plurality of the semiconductor chips outputs the first reception data from the first transmission terminals and further outputs the bit sequence from the second transmission terminals.

3. The semiconductor device according to claim 1 , wherein
the plurality of the semiconductor chips are three or more in number, and
each of the plurality of the semiconductor chips outputs the first reception data from the first transmission terminals and further converts the generated identification information by the inverse conversion method and then outputs the bit sequence from the second transmission terminals.

4. The semiconductor device according to claim 1 , wherein the reference data is a data that changes into different data when a value of each bit thereof is shifted towards a most significant bit side and a binary number overflowed from the most significant bit side is inserted into an empty bit that occurs on a least significant bit side;
the reference data is inputted into the first reception terminals that are arranged at one end of the semiconductor device; and
a source of the identification information is inputted into the second reception terminals that is arranged at the one end.

5. The semiconductor device according to claim 1 , wherein
the first reception terminals include a plurality of first points arranged in point symmetry around one point on the first face, and
the second reception terminals include a plurality of second points arranged in point symmetry around the one point on the first face, the plurality of the second points being different from the plurality of the first points.

6. The semiconductor device according to claim 1 , wherein
each of the first reception terminals is an electrode that is provided at one end of a through electrode that passes through one of the plurality of the semiconductor chips, and
each of the first transmission terminals is an electrode that is provided at another end of the through electrode.

7. The semiconductor device according to claim 1 , wherein
the reference data is a binary number, a least significant bit thereof being “1” and other bits thereof being “0”, and
wherein rightward-shift by m1 bit to the second reception data when the first reception data includes a bit a bit value of which is “1”, at m1-th bit counted from a least significant bit, the m1 being an integer.

8. The semiconductor device according to claim 1 , wherein
the reference data is a binary number, a least significant bit thereof being “0” and other bits thereof being “1”, and
wherein rightward-shift by m2 bit to the second reception data when the first reception data includes a bit a bit value of which is “0”, at m2-th bit counted from a least significant bit, the m2 being an integer.

9. The semiconductor device according to claim 1 , wherein the generating of the identification information involves adding a certain value or subtracting a certain value and is based on the second reception data.

10. The semiconductor device according to claim 1 , wherein each of the plurality of the semiconductor chips includes an internal circuit that operates based upon the identification information.

11. The semiconductor device according to claim 1 , wherein
the plurality of the semiconductor chips have one common structure, and
the another semiconductor chip is rotated relative to each of the plurality of the semiconductor chips.

12. The semiconductor device according to claim 1 , wherein
an n1-th bit of the first reception data is received at a first terminal of the first reception terminals, n1 being an integer equal to or greater than 0 and smaller than number of the first reception terminals;
an n1-th bit of a data outputted from the first transmission terminals is outputted from a second terminal of the first transmission terminals, the second terminal lying over the first terminal in a plane view;
the n2-th bit of the second reception data is received at a third terminal of the second reception terminals, n2 being an integer equal to or greater than 0 and smaller than number of the second reception terminals; and
an n2-th bit of a data outputted from the second transmission terminals is outputted from a fourth terminal of the second transmission terminals, the fourth terminal lying over the third terminal in a plane view.

13. A method of controlling a semiconductor device that includes a plurality of semiconductor chips that are stacked and further includes: first reception terminals of the plurality of the semiconductor chips, each of the first reception terminals being arranged in point symmetry on a first face; first transmission terminals of the plurality of the semiconductor chips, each of the first transmission terminals being arranged on a second face that is a back face of the first face, and each of the first transmission terminals lying over one of the first reception terminals of the plurality of the semiconductor chips in a plane view; and second reception terminals of the plurality of the semiconductor chips, each of the second reception terminals being arranged in point symmetry on the first face and the second reception terminals being different from the first reception terminals of the plurality of the semiconductor chips; each of the plurality of the semiconductor chips includes second transmission terminals of the plurality of the semiconductor chips, the second transmission terminals being arranged on the second face

Assignees

• Fujitsu Ltd

Inventors

• Hamada Yusuke

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title