Interposer and semiconductor package including the same

Patent metadata

Field	Value
Publication number	US-12087650-B2
Application number	US-202318315558-A
Country	US
Kind code	B2
Filing date	May 11, 2023
Priority date	Apr 13, 2020
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, the method comprising:
mounting a semiconductor chip on a package substrate;
disposing an interposer on the semiconductor chip, the interposer comprising
an interposer substrate comprising an upper conductive pad, and
a dam structure including an opening overlapping the upper conductive pad and extending along an edge of the upper conductive pad; and

forming a molding layer covering at least a portion of an upper surface of the interposer and at least a portion of the semiconductor chip,
wherein the forming of the molding layer comprises
disposing a molding film on the interposer to be in contact with an upper surface of the dam structure,
supplying a molding material into a space overlapping a lower surface of the molding film and the upper surface of the interposer substrate such that the molding material covers at least the portion of the upper surface of the interposer and at least the portion of the semiconductor chip,
hardening the molding material, and
removing the molding film.

2. The method of claim 1 , wherein, in the supplying of the molding material, the molding material is not supplied into the opening of the dam structure, and the molding material is not in contact with the upper conductive pad.

3. The method of claim 1 , wherein the dam structure comprises an insulating material.

4. The method of claim 1 , wherein the dam structure comprises a conductive material.

5. The method of claim 4 , wherein the molding layer includes an upper surface that is exposed by removing the molding film, and
the upper surface of the molding layer is coplanar with the upper surface of the dam structure.

6. The method of claim 1 , wherein
the interposer substrate comprises:
a lower surface facing the package substrate,
an upper surface in contact with the dam structure, and
a side wall; and

the molding layer comprises:
a lower portion extending along the lower surface of the interposer substrate,
an upper portion extending along the upper surface of the interposer substrate, and
a middle portion extending along the side wall of the interposer substrate.

7. The method of claim 1 , wherein a height of the dam structure is between 5 micrometers and 100 micrometers.

8. The method of claim 1 , wherein the dam structure is in contact with a portion of an upper surface of the upper conductive pad.

9. The method of claim 1 , further comprising:
forming a first conductive connector that fills the opening of the dam structure and is in contact with the upper conductive pad.

10. The method of claim 9 , wherein the dam structure comprises a first conductive material having a first melting point,
the upper conductive pad comprises a second conductive material having a second melting point, and
the first melting point is higher than the second melting point.

11. The method of claim 1 , wherein the interposer substrate is connected to the package substrate through a second conductive connector, and
the molding layer surrounds the second conductive connector.

12. A method of manufacturing a semiconductor package, the method comprising:
mounting a semiconductor chip on a package substrate;
disposing an interposer over the semiconductor chip, the interposer comprising an interposer substrate comprising an upper conductive pad and an insulating dam structure above an upper surface of the interposer substrate, the insulating dam structure extending along an edge of the upper conductive pad and having an opening overlapping the upper conductive pad such that at least a portion of an upper surface of the upper conductive pad is exposed through the opening; and
forming a molding layer covering at least a portion of the interposer and at least a portion of the semiconductor chip,
wherein the molding layer is formed to continuously extend along the upper surface and a side wall of the interposer substrate such that the molding layer includes a single material layer with a first region and a second region, the first region adjacent to the side wall of the interposer substrate and the second region above the first region, the second region including a bottom surface above and facing the upper surface of the interposer substrate.

13. The method of claim 12 , wherein
the insulating dam structure comprises:
an upper surface,
an outer wall in contact with the molding layer, and
an inner wall defining the opening; and

the molding layer is not in contact with the upper surface and the inner wall of the insulating dam structure.

14. The method of claim 13 , further comprising:
forming a conductive connector that fills the opening of the insulating dam structure and is in contact with the upper conductive pad,
wherein the conductive connector is in contact with the inner wall of the insulating dam structure.

15. The method of claim 13 , wherein
the molding layer is formed such that a thickness of the second region of the molding layer is less than or equal to a height of the insulating dam structure.

16. The method of claim 15 , wherein the height of the insulating dam structure is between 5 micrometers and 100 micrometers.

17. The method of claim 15 , wherein an upper surface of the molding layer is coplanar with an upper surface of the insulating dam structure.

18. The method of claim 12 , wherein the molding layer extends along a lower surface of the interposer substrate facing the package substrate, and
a portion of the molding layer is disposed between the semiconductor chip and a lower surface of the interposer substrate.

19. The method of claim 12 , wherein the forming of the molding layer comprises:
disposing a molding film on the interposer to be in contact with an upper surface of the insulating dam structure;
supplying a molding material into a space between the molding film and the interposer substrate;
hardening the molding material; and
removing the molding film, and
in the supplying of the molding material, the molding material is not supplied into the opening of the insulating dam structure.

20. The method of claim 12 , wherein the insulating dam structure includes solder resist.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Junyoung
• Baek Hyunggil
• Kim Seunghwan
• Kim Jungjoo
• Park Jongho
• Lee Yongkwan

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title