Packaged semiconductor devices and methods of packaging thereof

Patent metadata

Field	Value
Publication number	US-10269693-B2
Application number	US-201414471905-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Dec 13, 2012
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

First claim

What is claimed is:

1. A device, comprising:
a packaging apparatus;
a plurality of contact pads disposed on the packaging apparatus, the plurality of contact pads being arranged in an array of rows and columns, the plurality of contact pads comprising a plurality of first contact pads proximate a perimeter region of the packaging apparatus and a plurality of second contact pads disposed in an interior region of the packaging apparatus;
a first dam structure disposed around the plurality of second contact pads, wherein the first dam structure is continuous;
a first semiconductor device over the first dam structure and coupled to the first and second contact pads by a plurality of connectors, the first semiconductor device having a first side facing the first dam structure and a second side opposite the first side;
a second dam structure coupled to the first side of the first semiconductor device, the second dam structure vertically spaced apart from the first dam structure to prevent the first and second dam structures from directly contacting, the first semiconductor device having a third dam structure on the second side;
a second semiconductor device coupled to the first semiconductor device, the second semiconductor device comprising a fourth dam structure, the fourth dam structure interposed between the second side of the first semiconductor device and the second semiconductor device; and
a molding material disposed around one or more of the plurality of connectors and interposed between the first semiconductor device and the second semiconductor device, the molding material being a continuous region, the one or more of the plurality of connectors coupled to one or more of the first contact pads, the molding material contacting the one or more of the plurality of connectors and the first dam structure, the second dam structure having a most proximate surface to the first dam structure being free of molding material, the molding material contacting outermost sidewalls of the third dam structure and the fourth dam structure.

2. The device according to claim 1 , wherein the first dam structure comprises a substantially square, rectangle, or polygon shape in a top view.

3. The device according to claim 1 , wherein the plurality of first contact pads is arranged in a single row and a single column proximate the perimeter region of the packaging apparatus.

4. The device according to claim 1 , wherein the plurality of first contact pads is arranged in a plurality of rows or a plurality of columns proximate the perimeter region of the packaging apparatus on one side of the packaging apparatus.

5. The device according to claim 1 , wherein the packaging apparatus comprises a printed circuit board (PCB), an interposer substrate, or an integrated circuit die.

6. The device according to claim 1 , wherein the plurality of connectors comprise a first height, wherein the first dam structure comprises a second height, and wherein the second height comprises about 1/10 or greater than the first height.

7. A packaged semiconductor device, comprising:
a printed circuit board (PCB);
a plurality of contact pads disposed on the PCB, the plurality of contact pads being arranged in an array of rows and columns, the plurality of contact pads comprising a plurality of first contact pads proximate a perimeter region of the PCB and a plurality of second contact pads disposed in an interior region of the PCB;
a first dam structure disposed around the plurality of second contact pads between the plurality of second contact pads and the plurality of first contact pads, the first dam structure comprising a continuous ring;
a first partially packaged semiconductor device coupled to the plurality of contact pads by a first plurality of connectors, the first partially packaged semiconductor device comprising:
a first interconnect structure coupled to the first plurality of connectors,
an integrated circuit die coupled to the first interconnect structure,
a first molding material disposed around the integrated circuit die,
a plurality of through-vias disposed in the first molding material, and
a second interconnect structure disposed over the integrated circuit die, the first molding material, and the plurality of through-vias;
a plurality of third contact pads disposed on the second interconnect structure, the plurality of third contact pads being proximate a perimeter region of the second interconnect structure; and
a plurality of fourth contact pads disposed in an interior region of the second interconnect structure;

a second dam structure coupled to the first interconnect structure of the first partially packaged semiconductor device around connectors of the first plurality of connectors that are coupled to the plurality of second contact pads;
a second molding material or underfill material disposed around the plurality of first contact pads, the first dam structure, lower portions of edges of the first partially packaged semiconductor device, and connectors of the first plurality of connectors that are coupled to the plurality of first contact pads;
a third dam structure coupled to the second interconnect structure of the first partially packaged semiconductor device around the plurality of fourth contact pads, the third dam structure being between the plurality of third contact pads and the plurality of fourth contact pads;
a second partially packaged semiconductor device coupled to the first partially packaged semiconductor device by a second plurality of connectors disposed on the plurality of third contact pads and the plurality of fourth contact pads on the second interconnect structure; and
a fourth dam structure coupled to the second partially packaged semiconductor device, the fourth dam structure contacting the third dam structure, the fourth dam structure being bonded directly to the second partially packaged semiconductor device, the second molding material or underfill material contacting the third dam structure and the fourth dam structure.

8. The packaged semiconductor device according to claim 7 , wherein substantially no portion of the second molding material or the underfill material is disposed around the plurality of second contact pads within the first dam structure.

9. The packaged semiconductor device according to claim 7 , wherein the plurality of third and fourth contact pads on the second interconnect structure are arranged in an array of rows and columns, and wherein the third dam structure comprises a continuous ring.

10. The packaged semiconductor device according to claim 9 , wherein the fourth dam structure is disposed on a bottom surface of the second partially packaged semiconductor device, the fourth dam structure having a first sidewall coplanar with a second sidewall of the third dam structure.

11. The packaged semiconductor device according to claim 7 , wherein the first dam structure and the second dam structure are vertically aligned.

12. A packaged semiconductor device comprising:
a packaging apparatus having a first surface;
a plurality of contact pads over the packaging apparatus, the plurality of contact pads comprising a plurality of first contact pads proximate a perimeter region of the packaging apparatus and a plurality of second contact pads disposed in an interior region of the packaging apparatus;
a first dam structure on the first surface of the packaging apparatus, the first dam structure comprising a continuous ring around the plurality of second contact pads;
a first semiconductor device having a second surface facing the first surface of the packaging apparatus and a third surface opposite the second surface, the first semiconduc

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei

Classifications

• H05K1/181

  associated with surface mounted components · CPC title

• H05K2201/09409

  Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components · CPC title

• H05K3/40

  Forming printed elements for providing electric connections to or between printed circuits · CPC title

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H05K1/0313

  Organic insulating material · CPC title