Interposer and semiconductor package

Patent metadata

Field	Value
Publication number	US-9922924-B1
Application number	US-201615369834-A
Country	US
Kind code	B1
Filing date	Dec 5, 2016
Priority date	Nov 3, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

An interposer and a semiconductor package including the interposer are provided. The interposer includes a first dielectric layer, a conductive pillar, a conductive ring, a solder bump, and a redistribution layer. The first dielectric layer has an upper surface and a lower surface. The conductive pillar and the conductive ring are partially embedded in the first dielectric layer. A portion of the conductive pillar protrudes from the lower surface of the first dielectric layer. The conductive ring surrounds the conductive pillar, and a portion of the conductive ring protrudes from the lower surface of the first dielectric layer. The solder bump is disposed on the lower surface of the first dielectric layer, wherein the portion of the conductive pillar and the portion of the conductive ring are embedded in the solder bump. The redistribution layer is disposed on the upper surface of the first dielectric layer.

First claim

What is claimed is:

1. An interposer, comprising:
a first dielectric layer having an upper surface and a lower surface;
a conductive pillar partially embedded in the first dielectric layer, and a portion of the conductive pillar protruding from the lower surface of the first dielectric layer;
a conductive ring partially embedded in the first dielectric layer, the conductive ring surrounding the conductive pillar, and a portion of the conductive ring protruding from the lower surface of the first dielectric layer;
a solder bump on the lower surface of the first dielectric layer, wherein the portion of the conductive pillar and the portion of the conductive ring are embedded in the solder bump; and
a redistribution layer disposed on the upper surface of the first dielectric layer.

2. The interposer of claim 1 , wherein a portion of the first dielectric layer surrounds the conductive pillar to separate the conductive pillar and the conductive ring.

3. The interposer of claim 1 , further comprising a conductive connector embedded in the first dielectric layer, wherein the conductive connector connects the conductive pillar and the conductive ring.

4. The interposer of claim 1 , wherein a material of the conductive pillar is same as a material of the conductive ring.

5. The interposer of claim 1 , wherein the redistribution layer comprises a second dielectric layer and an interconnect structure embedded in the second dielectric layer.

6. The interposer of claim 5 , wherein the conductive pillar penetrates through the first dielectric layer and is disposed in contact with the interconnect structure.

7. The interposer of claim 5 , wherein the conductive ring penetrates through the first dielectric layer and is disposed in contact with the second dielectric layer.

8. The interposer of claim 5 , wherein the conductive ring penetrates through the first dielectric layer and is disposed in contact with the interconnect structure.

9. The interposer of claim 5 , further comprising a microbump disposed on the redistribution layer, wherein the microbump is disposed in contact with the interconnect structure.

10. The interposer of claim 1 , wherein the conductive pillar has a surface coplanar with the upper surface of the first dielectric layer.

11. The interposer of claim 1 , wherein the conductive ring has a surface coplanar with the upper surface of the first dielectric layer.

12. The interposer of claim 1 , wherein a first height of the conductive pillar is larger than, equal to, or smaller than a second height of the conductive ring.

13. The interposer of claim 1 , wherein a height of the conductive ring is larger than a thickness of the first dielectric layer.

14. The interposer of claim 1 , wherein the conductive ring is circular ring-shaped, polygonal ring-shaped, or irregular ring-shaped.

15. The interposer of claim 1 , wherein a material of the conductive pillar comprises copper, chromium, nickel, aluminum, gold, silver, tungsten, titanium, tin, platinum, palladium, titanium nitride (TIN), titanium tungsten (TiW), nickel vanadium (NiV), or chromium copper (CrCu).

16. The interposer of claim 1 , wherein a material of the conductive ring comprises copper, chromium, nickel, aluminum, gold, silver, tungsten, titanium, tin, platinum, palladium, titanium nitride (TiN), titanium tungsten (TiW), nickel vanadium (NiV), or chromium copper (CrCu).

17. A semiconductor package, comprising:
the interposer of claim 1 ;
a microbump disposed on the redistribution layer; and
a chip disposed on the microbump, wherein the redistribution layer comprises a second dielectric layer and an interconnect structure embedded in the second dielectric layer, and the microbump is disposed in contact with the interconnect structure.

18. The semiconductor package of claim 17 , wherein a portion of the first dielectric layer surrounds the conductive pillar to separate the conductive pillar and the conductive ring.

19. The semiconductor package of claim 17 , further comprising a conductive connector embedded in the first dielectric layer, wherein the conductive connector connects the conductive pillar and the conductive ring.

20. The semiconductor package of claim 17 , wherein the conductive ring penetrates through the first dielectric layer and is disposed in contact with the second dielectric layer.

Assignees

• Micron Technology Inc

Inventors

• Shih Shing-Yih

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title