Memory cell structure of a three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-12063780-B2
Application number	US-202117465231-A
Country	US
Kind code	B2
Filing date	Sep 2, 2021
Priority date	Aug 28, 2017
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
an alternating conductor/dielectric stack disposed on a substrate, wherein the alternating conductor/dielectric stack comprises a dielectric layer and a conductive layer stacked in a vertical direction;
a plurality of channel holes formed on the substrate penetrating the alternating conductor/dielectric stack;
a channel structure in each channel hole; and
a plurality of gate line slits disposed on the substrate, wherein:
the plurality of channel holes are perpendicular to the substrate and are arranged in a hexagonal lattice orientation comprising a plurality of hexagons;
each hexagon comprises three pairs of sides, wherein a first pair is perpendicular to a first direction and parallel to a second direction, and wherein the second direction is perpendicular to the first direction; and
the plurality of gate line slits extend vertically through the dielectric layer and the conductive layer.

2. The 3D memory device of claim 1 , wherein the three pairs of sides further include a second pair of sides, and a third pair of sides, and wherein the plurality of gate line slits are parallel to the second and the third pairs of sides of each hexagon of the hexagonal lattice.

3. The 3D memory device of claim 1 , wherein the channel structure comprises a semiconductor channel and a memory film.

4. The 3D memory device of claim 1 , further comprising:
a top select gate structure, wherein the top select gate is parallel to a gate line slit, forming a zigzag pattern extending in the first direction.

5. The 3D memory device of claim 1 , wherein the plurality of gate line slits form a zigzag pattern extending in the first direction.

6. The 3D memory device of claim 1 , wherein the plurality of channel holes are disposed at vertices and centers of the hexagons.

7. The 3D memory device of claim 6 , wherein channel holes disposed at the centers of the hexagons comprise a same distance to adjacent channel holes disposed at the vertices of the hexagons.

8. The 3D memory device of claim 1 , further comprising:
a bit line configured to electrically connect with the channel structure and forming an angle of about 30 degrees with respect to the second direction.

9. A three-dimensional (3D) memory device, comprising:
an alternating conductor/dielectric stack disposed on a substrate, wherein the alternating conductor/dielectric stack comprises a dielectric layer and a conductive layer stacked in a vertical direction;
a plurality of channel structures extending vertically through the alternating conductor/dielectric stack, wherein:
the plurality of channel structures are arranged in a hexagonal lattice;
the hexagonal lattice comprises a plurality of hexagons, each hexagon comprising three pairs of sides; and
a first pair of sides are parallel to a first direction and perpendicular to a second direction, and wherein the first direction is perpendicular to the second direction; and

a slit extending vertically through the dielectric layer and the conductive layer, wherein the slit is parallel to the first direction.

10. The 3D memory device of claim 9 , further comprising:
a plurality of bit lines configured to electrically connect with the plurality of channel structures.

11. The 3D memory device of claim 10 , wherein the plurality of bit lines are perpendicular to the slit and parallel to the second direction.

12. The 3D memory device of claim 11 , further comprising:
a plurality of bit line contacts wherein a spacing between two neighboring bit line contacts along the first direction is twice that of a spacing between two neighboring bit lines.

13. The 3D memory device of claim 12 , wherein the plurality of bit line contacts are arranged in the hexagonal lattice.

14. The 3D memory device of claim 9 , wherein each channel structure of the plurality of channel structures comprises a semiconductor channel and a memory film.

15. The 3D memory device of claim 9 , wherein the plurality of channel structures are disposed at vertices and centers of the plurality of hexagons.

16. The 3D memory device of claim 15 , wherein channel structures disposed at the centers of the plurality of hexagons comprise a same distance to adjacent channel structures disposed at the vertices of the plurality of hexagons.

17. A three-dimensional (3D) memory device, comprising:
NAND strings vertically stacked on a substrate, wherein:
the NAND strings are arranged as a hexagonal lattice, wherein the NAND strings are disposed at vertices and centers of hexagons of the hexagonal lattice; and
the hexagons of the hexagonal lattice each comprise a first pair of sides, a second pair of sides, and a third pair of sides, wherein the first pair of sides are perpendicular to a first direction; and
gate line slits extending parallel to the first direction and configured to divide the 3D memory device into multiple memory fingers, wherein the gate line slits are parallel to the second and the third pairs of sides of each hexagon of the hexagonal lattice.

18. The 3D memory device of claim 17 , wherein the NAND strings disposed at the centers of the hexagons comprise a same distance to the NAND strings disposed at the vertices of the hexagons.

19. The 3D memory device of claim 17 , wherein each of the NAND strings extends vertically through an alternating conductor/dielectric stack disposed on the substrate.

20. The 3D memory device of claim 19 , wherein each of the NAND strings comprises a semiconductor channel and a memory film.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Dai Xiaowang
• Lu Zhenyu
• Chen Jun
• Tao Qian
• Hu Yushi
• Zhu Jifeng
• Dong Jin Wen
• Xia Ji
• Zhang Zhong
• Li yan ni

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title