Semiconductor device

Patent metadata

Field	Value
Publication number	US-9553101-B2
Application number	US-201414258772-A
Country	US
Kind code	B2
Filing date	Apr 22, 2014
Priority date	Jun 27, 2013
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of gate structures spaced apart above a top surface of a substrate, the plurality of gate structures including a horizontal electrode extending in a first direction parallel with the top surface of the substrate;
an isolation insulating material disposed between the gate structures; and
a plurality of cell pillars penetrating the horizontal electrode to be spaced apart from each other, each of the cell pillars surrounded by the horizontal electrode,
wherein a vertical thickness of the horizontal electrode is greater than a first spacing defined by a shortest horizontal distance between any two of the plurality of the cell pillars.

2. The semiconductor device of claim 1 , wherein the thickness of the horizontal electrode is greater than a second spacing of the cell pillars defined by a shortest distance between two adjacent cell pillars of the plurality of cell pillars that are nearest to the isolation insulating material.

3. The semiconductor device of claim 2 , wherein the second spacing of the cell pillars is greater than the first spacing of the cell pillars.

4. The semiconductor device of claim 1 , wherein the plurality of cell pillars includes first cell pillars nearest to the isolation insulating material and second cell pillars next nearest to the isolation insulating material.

5. The semiconductor device of claim 4 , wherein the first cell pillars and the second cell pillars are arranged in a zigzag.

6. The semiconductor device of claim 4 , wherein a distance between a pair of immediately adjacent first cell pillars is equal to or greater than a distance between a pair of immediately adjacent second cell pillars.

7. The semiconductor device of claim 4 , wherein a diameter of a first cell pillar is less than a diameter of a second cell pillar.

8. The semiconductor device of claim 6 , wherein the distance between the pair of immediately adjacent first cell pillars is greater than a distance between one of the first cell pillars and one of the second cell pillars nearest to the one of the first cell pillars.

9. The semiconductor device of claim 4 , further comprising:
a plurality of third pillars third-nearest to the isolation insulating material; and
wherein the first cell pillars, second cell pillars, and third pillars are arranged in a zigzag.

10. The semiconductor device of claim 9 , wherein a distance between one of the second cell pillars and one of the first cell pillars nearest thereto is greater than a distance between one of the second cell pillars and one of the third pillars nearest thereto.

11. A semiconductor device comprising:
gate structures disposed above a substrate, each of the gate structures including vertically stacked horizontal electrodes and insulating patterns between the horizontal electrodes;
a first isolation insulating layer disposed between the gate structures; and
a plurality of cell pillars penetrating the gate structures to be spaced apart from each other, each of the cell pillars surrounded by the horizontal electrode,
wherein a vertical thickness of each of the horizontal electrodes in the gate structures is greater than a horizontal distance between adjacent cell pillars where the cell pillars penetrate the horizontal electrode.

12. The semiconductor device of claim 11 , wherein each of the gate structures includes horizontally spaced apart first and second uppermost horizontal electrodes.

13. The semiconductor device of claim 12 , further comprising:
a second isolation insulating layer filling a trench between the first and second uppermost horizontal electrodes, the trench extending from a top surface of the gate structure to the substrate through the vertically stacked horizontal electrodes.

14. The semiconductor device of claim 13 , wherein the trench is provided between cell pillars in a center portion of each of the gate structures; and
wherein a distance between the second isolation insulating layer and a cell pillar nearest to the second isolation insulating layer is less than a distance between a pair of immediately adjacent cell pillars.

15. A semiconductor device comprising:
gate structures disposed above a substrate, each of the gate structures including vertically stacked horizontal electrodes and insulating patterns between the horizontal electrodes;
a first isolation insulating layer disposed between the gate structures;
a plurality of cell pillars penetrating the gate structures to be spaced apart from each other, each of the cell pillars surrounded by the horizontal electrode,
wherein a vertical thickness of each of the horizontal electrodes in the gate structures is greater than a horizontal distance between adjacent cell pillars where the cell pillars penetrate the horizontal electrode, and
wherein each of the gate structures includes horizontally spaced apart first and second uppermost horizontal electrodes; and
dummy pillars extending to the substrate through the gate structures between the horizontally spaced apart first and second uppermost horizontal electrodes.

16. The semiconductor device of claim 15 , wherein the dummy pillars are disposed between the cell pillars in a center portion of each of the gate structures; and
wherein the dummy pillars and the cell pillars adjacent thereto are arranged in a zigzag.

17. The semiconductor device of claim 16 , wherein a distance between one of the dummy pillars and one of the cell pillars nearest to the one of the dummy pillars is less than a distance between a pair of immediately adjacent cell pillars.

18. The semiconductor device of claim 11 , wherein the cell pillars are semiconductor pillars, and the semiconductor device further comprises:
a charge storage element between each of the semiconductor pillars and each of the horizontal electrodes.

19. The semiconductor device of claim 18 , wherein the charge storage element comprises: a charge storage layer; a blocking insulating layer between the charge storage layer and each of the horizontal electrodes; and a tunnel insulating layer between the charge storage layer and each of the semiconductor pillars.

20. The semiconductor device of claim 19 , further comprising:
a common source line provided in the substrate overlapping with the first isolation insulating layer; and
a bit line coupled to the cell pillars.

21. The semiconductor device of claim 11 , wherein the cell pillars are conductive pillars, and the semiconductor device further comprises:
a charge storage element between each of the conductive pillars and each of the horizontal electrodes,
wherein the charge storage element is a variable resistance pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Taekyung
• Seol Kwang Soo
• Back Hyunchul
• Lim Jin-Soo
• Cho Seong Soon

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H01L45/06

  Electricity · mapped topic

• H01L45/1226

  Electricity · mapped topic