Semiconductor memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9520407-B2
Application number	US-201514614588-A
Country	US
Kind code	B2
Filing date	Feb 5, 2015
Priority date	Feb 6, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a connecting member including a semiconductor material;
a first electrode film provided at least above the connecting member;
a first insulating film provided on the first electrode film;
a stacked body provided on the first insulating film, the stacked body including second electrode films and second insulating films, each of the second electrode films and each of the second insulating films being alternately stacked;
three or more semiconductor pillars arrayed along two or more directions different from one another, extending in a stacking direction of the second electrode films and the second insulating films, piercing through the stacked body and the first insulating film, and connected to the connecting member;
a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film; and
a charge storage layer provided at least between one of the second electrode films and the third insulating film,
the semiconductor pillars and the connecting member being integrally formed.

2. The device according to claim 1 , wherein through-holes extending in the stacking direction are formed in the connecting member.

3. The device according to claim 2 , wherein the through-holes are periodically arrayed.

4. The device according to claim 2 , wherein parts of the first electrode film is disposed in the through-holes.

5. The device according to claim 1 , further comprising:
interconnection members extending through the stacked body and the first insulating film, at least one of the interconnection members being connected to the connecting member; and
a fourth insulating film provided between one of the interconnection members and the stacked body.

6. The device according to claim 5 , wherein
lower sections of the interconnection members include a semiconductor material;
upper sections of the interconnection members include metal, and
effective impurity concentration in one of the lower sections of the interconnection members is higher than effective impurity concentration in the connecting member.

7. The device according to claim 5 , wherein
the interconnection members include metal, and
effective impurity concentration in a portion of the connecting member in contact with one of the interconnection members is higher than effective impurity concentration in a portion of the connecting member in contact with one of the semiconductor pillars.

8. The device according to claim 5 , wherein one of the interconnection members includes:
a core section including metal; and
a peripheral section covering a lower surface and a side surface of the core section and including a semiconductor material.

9. The device according to claim 8 , wherein the peripheral section includes silicide of the metal.

10. The device according to claim 5 , further comprising a third electrode film provided between the first electrode film and the stacked body and between the interconnection members, and extending in a first direction orthogonal to the stacking direction.

11. The device according to claim 5 , wherein an n-type semiconductor portion or a p-type semiconductor portion in contact with the connecting member is formed in a lower section of one of the interconnection members.

12. The device according to claim 5 , wherein
n-type semiconductor portions are disposed in portions in the connecting member in contact with some of the interconnection members, and
p-type semiconductor portions are disposed in portions in the connecting member in contact with some of the interconnection members.

13. The device according to claim 12 , wherein
the interconnection members are arrayed spaced from one another along a second direction orthogonal to both of the stacking direction and a first direction, the first direction is orthogonal to the stacking direction, and
each of the n-type semiconductor portions and each of the p-type semiconductor portions are alternately disposed along the second direction in regions directly under the interconnection members.

14. The device according to claim 12 , wherein
the interconnection members are arrayed spaced from one another along a second direction orthogonal to both of the stacking direction and the first direction,
each of the n-type semiconductor portions and each of the p-type semiconductor portions are alternately disposed along the second direction,
the n-type semiconductor portions are disposed in regions directly under the interconnection members, and
the p-type semiconductor portions are not disposed in regions directly under the interconnection members.

15. The device according to claim 12 , wherein
the n-type semiconductor portions and the p-type semiconductor portions are spaced from each other, and
some of the interconnection members connected to the n-type semiconductor portions and some of the interconnection members connected to the p-type semiconductor portions are insulated from each other.

16. The device according to claim 5 , wherein an n-type semiconductor portion and a p-type semiconductor portion are disposed in a portion in the connecting member in contact with one of the interconnection members.

Assignees

• Toshiba Kk

Inventors

• Fukuzumi Yoshiaki
• Arai Shinya
• Tsuji Masaki
• Aochi Hideaki
• Tanaka Hiroyasu

Classifications

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/0413 Primary

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic