Pillar arrangement in NAND memory

Patent metadata

Field	Value
Publication number	US-9553099-B2
Application number	US-201615232762-A
Country	US
Kind code	B2
Filing date	Aug 9, 2016
Priority date	Mar 24, 2015
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the apparatus may comprise a substantially hexagonal arrangement having seven pillars disposed in a die in a repeating pattern. The arrangement may include first and second pillars disposed at a pillar pitch from each other in a first row; third, fourth, and fifth pillars disposed at the pillar pitch from each other in a second row; and sixth and seventh pillar disposed at the pillar pitch from each other in a third row and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a direction that is substantially orthogonal to bitlines disposed in the die. Each pillar in the arrangement may be electrically coupled with a different bitline. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A method, comprising:
disposing a plurality of bitlines in a die;
disposing a substantially hexagonal arrangement having seven pillars in the die, including:
disposing first and second pillars at a pillar pitch from each other in a first row of the arrangement;
disposing third, fourth, and fifth pillars at the pillar pitch from each other in a second row of the arrangement;
disposing sixth and seventh pillars at the pillar pitch from each other in a third row of the arrangement and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a first direction that is substantially orthogonal to the plurality of bitlines disposed in the die, and shifted relative to the third and fourth pillars by the quarter of the pillar pitch in a second direction that is substantially orthogonal to the plurality of bitlines, wherein each pillar in the arrangement is electrically coupled with a different bitline of the plurality of bitlines, wherein the second row is located between the first and third rows; and
electrically coupling each of the pillars in the arrangement with a drain-side select gate (SGD); and

electrically coupling each pillar in the arrangement with a different bitline of the plurality of bitlines.

2. The method of claim 1 , further comprising: repeating the disposing of the arrangement in the die, to provide a structure comprising a three-dimensional (3D) memory array.

3. The method of claim 2 , wherein the structure comprises a 3D NAND memory array.

4. The method of claim 1 , wherein disposing a plurality of bitlines in a die includes disposing the bitlines at least half of a characteristic bitline pitch from each other.

5. The method of claim 1 , wherein disposing the first, second, third, fourth, fifth, sixth, and seventh pillars includes disposing the first and second rows at a first distance from each other, and disposing the second and third rows at a second distance from each other, wherein the second distance is different from the first distance.

6. The method of claim 5 , wherein the first and second distances are selected to provide a desired spacing between the pillars of the arrangement.

7. A method for providing a memory device, comprising:
providing a first pillar grouping of a plurality of pillars in a die, wherein providing includes disposing a second pillar at a pillar pitch from a first pillar along a first imaginary line that is substantially orthogonal to first and second bitlines, electrically coupling the first pillar with a first bitline, and electrically coupling the second pillar with a second bitline, and
providing a second pillar grouping of the plurality of pillars in the die, wherein providing includes shifting a third pillar by a quarter of the pillar pitch from the first pillar along a second imaginary line that is substantially orthogonal to the bitlines, and electrically coupling the third pillar with a third bitline; and disposing a fourth pillar to be placed at the pillar pitch from the third pillar and shifted by the quarter of the pillar pitch from the second pillar along the second imaginary line, and electrically coupling the fourth pillar with a fourth bitline,
wherein providing the first pillar grouping further includes disposing a sixth pillar to be placed at the pillar pitch from a fifth pillar along a third imaginary line that is substantially orthogonal to the first and second bitlines, and electrically coupling the fifth pillar with a fifth bitline, and electrically coupling the sixth pillar with a sixth bitline, wherein the third imaginary line is located between the first and second imaginary lines,
wherein providing the second pillar grouping further includes shifting a seventh pillar by the quarter of the pillar pitch from the fifth pillar along a fourth imaginary line that is substantially orthogonal to the first and second bitlines, and electrically coupling the seventh pillar with a seventh bitline; and disposing an eighth pillar to be placed at the pillar pitch from the seventh pillar and shifted by the quarter of the pillar pitch from the sixth pillar along the fourth imaginary line, and electrically coupling the eighth pillar with an eighth bitline, wherein the second imaginary line is located between the third and fourth imaginary lines, and
coupling the first and second pillar groupings with a drain-side select gate (SGD) line.

8. The method of claim 7 , wherein the first and second imaginary lines are disposed at a first distance from each other.

9. The method of claim 8 , wherein the second and third imaginary lines are disposed at a second distance from each other, wherein the second distance is different from the first distance.

10. The method of claim 7 , further comprising: disposing the first and fifth bitlines at a characteristic bitline pitch from each other, disposing the first and sixth bitlines at the characteristic bitline pitch from each other, and disposing the sixth and second bitlines at the characteristic bitline pitch from each other.

11. The method of claim 10 , further comprising: disposing the third bitline between the fifth and first bitlines at a half of the characteristic bitline pitch from the fifth and first bitlines, and disposing the fourth bitline between the sixth and second bitlines at the half of the characteristic bitline pitch from the sixth and second bitlines.

12. The method of claim 7 , wherein the memory device comprises a three-dimensional (3D) memory array.

Assignees

• Intel Corp

Inventors

• Wolstenholme Graham Richard

Classifications

• H01L27/11551 Primary

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title