Three-dimensional memory and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-12052871-B2
Application number	US-202117496031-A
Country	US
Kind code	B2
Filing date	Oct 7, 2021
Priority date	Aug 29, 2019
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the method for forming the 3D memory device includes forming an alternating dielectric stack on a substrate, and forming channel holes that penetrate the alternating dielectric stack and expose at least a portion of the substrate. The method further includes forming top select gate openings that penetrate vertically an upper portion of the alternating dielectric stack and extend laterally. The method also includes forming slit openings parallel to the top select gate openings, wherein the slit openings penetrate vertically the alternating dielectric stack. The method also includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers, forming top select gate cuts in the top select gate openings, and forming slit structures in the slit openings.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a film stack of alternating conductive and dielectric layers disposed on a substrate;
memory strings and slit structures extending in a first direction perpendicular to the substrate, penetrating through the film stack of alternating conductive and dielectric layers, wherein:
the slit structures extend laterally in a second direction parallel to the substrate; and
the memory strings are arranged in rows, each row of memory strings being staggered from adjacent rows of memory strings; and

at least two top select gate cuts disposed between adjacent slit structures and filled with an insulating film, wherein each top select gate cut of the at least two select gate cuts:
comprises a width smaller than a diameter of the memory strings;
penetrates through an upper portion of the film stack in the first direction; and
extends parallel to the slit structures.

2. The 3D memory device of claim 1 , wherein the insulating film covers sidewalls of the slit structures.

3. The 3D memory device of claim 2 , wherein at least one of the slit structures further comprises a conductive core, and wherein the conductive core is in contact with a doped region within the substrate.

4. The 3D memory device of claim 1 , wherein the slit structures extend between the rows of memory strings and are configured to divide a memory block into memory fingers.

5. The 3D memory device of claim 4 , wherein the top select gate cuts are configured to divide each memory finger into memory slices, each memory slice comprising two or more rows of the memory strings.

6. The 3D memory device of claim 5 , wherein each memory slice is controlled independently by a top select gate formed by the conductive layers in the upper portion of the film stack.

7. A three-dimensional (3D) memory device, comprising:
a film stack of alternating conductive and dielectric layers disposed on a substrate;
memory strings penetrating through the film stack in a first direction perpendicular to the substrate;
a slit structure penetrating through the film stack in the first direction and extending in a second direction parallel to the substrate; and
at least two top select gate cuts penetrating through an upper portion of the film stack in the first direction and extending in the second direction, wherein each top select gate cut of the at least two top select gate cuts comprises an insulating film of a same material and a width smaller than a diameter of the memory strings.

8. The 3D memory device of claim 7 , wherein the film stack comprises conductive and dielectric layer pairs, and wherein each conductive and dielectric pair comprises a dielectric layer and a conductive layer.

9. The 3D memory device of claim 8 , wherein the top select gate cuts penetrate through a top three conductive and dielectric pairs of the film stack.

10. The 3D memory device of claim 7 , wherein the top select gate cuts are filled with the insulating film.

11. The 3D memory device of claim 7 , wherein the insulating film covers a sidewall of the slit structure.

12. The 3D memory device of claim 7 , wherein the insulating film comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

13. The 3D memory device of claim 7 , wherein the slit structure further comprises a conductive core, and wherein the conductive core is in contact with a doped region within the substrate.

14. The 3D memory device of claim 13 , wherein the conductive core comprises tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, polycrystalline silicon, or a combination thereof.

15. The 3D memory device of claim 7 , wherein each of the memory strings comprises:
a core filling film disposed in a center of each of the memory strings;
a channel layer covering a sidewall of the core filling film; and
a memory film covering a sidewall of the channel layer.

16. The 3D memory device of claim 7 , wherein the memory strings are arranged in rows on a plane parallel to the substrate, each row of memory strings being staggered from adjacent rows of memory strings.

17. The 3D memory device of claim 16 , wherein the slit structure and the top select gate cuts extend between the rows of memory strings and are distant from the memory strings.

18. The 3D memory device of claim 16 , wherein the slit structure is configured to divide a memory block into memory fingers.

19. The 3D memory device of claim 16 , wherein the top select gate cuts are configured to divide each memory finger into memory slices, each memory slice comprising two or more rows of memory strings.

20. The 3D memory device of claim 7 , wherein the top select gate cuts extend in the second direction with a wavy shape.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xia Ji
• Huo Zongliang
• Zhou Wenbin
• Xu Wei
• Huang Pan
• Xu Wenxiang

Classifications

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title