Three-dimensional memory device having drain select level isolation structure and method of making thereof

Patent metadata

Field	Value
Publication number	US-10050054-B2
Application number	US-201615286063-A
Country	US
Kind code	B2
Filing date	Oct 5, 2016
Priority date	Oct 5, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.

First claim

What is claimed is:

1. A method of forming a three-dimensional memory device, comprising:
forming a layer stack over a substrate, wherein the layer stack comprises an alternating stack of insulating layers and sacrificial material layers;
forming memory stack structures through the alternating stack;
forming a backside trench through the alternating stack;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers;
forming electrically conductive layers in the backside recesses;
forming a dielectric isolation structure in drain select level of the three-dimensional memory device after formation of the electrically conductive layers;
forming an isolation trench through the drain select level, wherein the dielectric isolation structure is formed in the isolation trench and wherein the drain select level comprises a set of layers including the topmost electrically conductive layer among the electrically conductive layers which comprises a drain select gate;
depositing and removing at least one metallic fill material layer in the isolation trench prior to formation of the dielectric isolation structure in the isolation trench, wherein portions of the at least one metallic fill material layer deposited in the backside recesses constitute the electrically conductive layers;
depositing the at least one metallic fill material layer in the isolation trench to fill the isolation trench; and
removing a portion of the at least one metallic fill material layer from within the isolation trench, wherein the dielectric isolation structure is formed in a volume from which the portion of the at least one metallic fill material layer is removed.

2. The method of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

3. A method of forming a three-dimensional memory device, comprising:
forming a layer stack over a substrate, wherein the layer stack comprises an alternating stack of insulating layers and sacrificial material layers;
forming memory stack structures through the alternating stack;
forming a backside trench through the alternating stack;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers;
forming electrically conductive layers in the backside recesses;
forming a dielectric isolation structure in drain select level of the three-dimensional memory device after formation of the electrically conductive layers; and
forming an isolation trench through the drain select level, wherein the dielectric isolation structure is formed in the isolation trench;
wherein:
the drain select level comprises an additional electrically conductive layer which comprises a drain select gate which is formed after formation of the electrically conductive layers;
the layer stack further comprises an additional material layer overlying the alternating stack; and
the additional electrically conductive layer is formed by replacing or modifying the additional material layer by introducing a conductive material through the isolation trench.

4. The method of claim 3 , wherein:
the additional material layer comprises a material different from materials of the insulating layers and the sacrificial material layers; and
the additional material layer is replaced or modified after formation of the electrically conductive layers.

5. The method of claim 4 , wherein the additional material layer is replaced with the additional electrically conductive layer by:
introducing an etchant that removes the additional material layer selective to the insulating layers to form additional lateral recesses; and
depositing a conductive material in the additional lateral recesses.

6. The method of claim 4 , wherein:
the additional material layer comprises a semiconductor material; and
the additional material layer is modified into a metal-semiconductor alloy layer by reacting with a metal deposited on the additional material layer through the isolation trench.

7. The method of claim 6 , further comprising forming at least one air gap by depositing a dielectric material employing a conformal deposition process during formation of the dielectric isolation structure.

8. The method of claim 6 , further comprising forming a dielectric material layer directly on the metal-semiconductor alloy layer during formation of the dielectric isolation structure.

9. The method of claim 3 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Alsmeier Johann
• Makala Raghuveer S
• Kanakamedala Senaka
• Sharangpani Rahul
• Kai James

Classifications

• H01L27/11519

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic