Memory device and method for manufacturing memory device

US10319740B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10319740-B2
Application numberUS-201815917954-A
CountryUS
Kind codeB2
Filing dateMar 12, 2018
Priority dateAug 31, 2017
Publication dateJun 11, 2019
Grant dateJun 11, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.

First claim

Opening claim text (preview).

What is claimed is: 1. A memory device comprising: a first conductive layer extending along a first direction; a second conductive layer being distant from the first conductive layer in a second direction crossing the first direction and extending along the first direction; a first semiconductor member extending in a third direction crossing a plane including the first direction and the second direction, and passing through between the first conductive layer and the second conductive layer; a second semiconductor member extending in the third direction and passing through between the first semiconductor member and the second conductive layer; a first charge storage member provided between the first conductive layer and the first semiconductor member; a first insulating member provided between the first conductive layer and the first charge storage member; a first insulating layer including a first region and a second region, the first region being positioned between the first semiconductor member and the first charge storage member, the second region being positioned between the first semiconductor member and the second semiconductor member; a second charge storage member provided between the second conductive layer and the second semiconductor member; a second insulating member provided between the second conductive layer and the second charge storage member; and a second insulating layer including a third region and a fourth region, the third region being positioned between the second semiconductor member and the second charge storage member, the fourth region being positioned between the second region and the second semiconductor member, wherein the first semiconductor member and the second semiconductor member are non-linear in the third direction. 2. The device according to claim 1 , further comprising: an insulating part including a first insulating region and a second insulating region, at least a part of the first insulating region being positioned between the second region and the fourth region, a direction from the second insulating region toward the first semiconductor member being along the first direction, and a material included in the second insulating region being different from a material included in the first insulating region. 3. The device according to claim 1 , further comprising: third to sixth semiconductor members extending along the third direction, a direction from the first semiconductor member toward the third semiconductor member being along the first direction, a direction from the second semiconductor member toward the fourth semiconductor member being along the first direction, a position of the first conductive layer in the second direction being positioned between a position of the first semiconductor member in the second direction and a position of the fifth semiconductor member in the second direction, a position of the second conductive layer in the second direction being positioned between a position of the second semiconductor member in the second direction and a position of the sixth semiconductor member in the second direction, a position of the fifth semiconductor member in the first direction being positioned between a position of the first semiconductor member in the first direction and a position of the second semiconductor member in the first direction, and a position of the sixth semiconductor member in the first direction being positioned between the position of the first semiconductor member in the first direction and the position of the second semiconductor member in the first direction. 4. The device according to claim 1 , wherein a direction from the first charge storage member toward a part of the first conductive layer is along the first direction, and a direction from the second charge storage member toward a part of the second conductive layer is along the first direction. 5. The device according to claim 1 , further comprising: a conductive base member electrically connected to the first semiconductor member and the second semiconductor member, the first semiconductor member having a first surface opposing the first charge storage member, the second semiconductor member having a second surface opposing the second charge storage member, and a space between the first surface and the second surface changing depending on a position being distant from the conductive base member in the third direction. 6. The device according to claim 2 , wherein the insulating part further includes a third insulating region, the first semiconductor member passes through between the second insulating region and the third insulating region, and a material included in the third insulating region is different from a material included in the second insulating region. 7. A method for manufacturing a memory device comprising: forming a first structural body and a second structural body, the first structural body extending along a first direction, the second structural body extending along the first direction, the second structural body being distant from the first structural body along a second direction crossing the first direction, the first structural body including a first film, the second structural body including a second film; forming a third structural body including a first material insulating part, a second material insulating part and a third material insulating part, the first material insulating part being positioned between the first structural body and the second structural body in the second direction, the second material insulating part being positioned between the first material insulating part and the second structural body in the second direction, the third material insulating part being positioned between the first material insulating part and the second material insulating part, a third material of the third material insulating part being different from a first material of the first material insulating part and being different from a second material of the second material insulating part; forming a first hole in the third structural body by removing a part of the first material insulating part, a part of the second material insulating part, and a part of the third material insulating part; forming a fourth structural body having a second hole by forming a film of a fourth material in the first hole after recessing the first material insulating part and the second material insulating part exposed to the first hole; forming a third hole by removing a part of the fourth structural body, a first residual portion and a second residual portion of the fourth structural body remaining in the third hole; forming a fifth structural body from a fifth material by burying the fifth material in the third hole; forming a fourth hole and a fifth hole by removing the first residual portion and the second residual portion after forming the fifth structural body; and forming a first functional film in the first film and the second film exposed to the fourth hole and the fifth hole, respectively, wherein the first structural body and the second structural body member are non-linear in a third direction crossing a plane including the first direction and the second direction. 8. The method according to claim 7 , further comprising: forming a first member in a residual space of the fourth hole and a residual space of the fifth hole, the first member including a conductive member extending along the third direction or a semiconductor member. 9. The method according to claim 7 , wherein the first film and the second film exposed to the fourth hole and the fifth hole are recessed after the forming the fourth hole and the fifth hole and before the forming the first fun

Assignees

Inventors

Classifications

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material containing aluminium, e.g. Al2O3 · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • by chemical means · CPC title

  • using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

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What does patent US10319740B2 cover?
A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second se…
Who is the assignee on this patent?
Toshiba Memory Corp
What technology area does this patent fall under?
Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 11 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).