Variable resistance memory device

Patent metadata

Field	Value
Publication number	US-12051455-B2
Application number	US-202217845274-A
Country	US
Kind code	B2
Filing date	Jun 21, 2022
Priority date	Oct 7, 2021
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A variable resistance memory device includes active regions apart from each other, common bit line contacts in the active regions, first active source contacts on first active regions near one edge of each of the common bit line contacts, second active source contacts on second active regions near another edge of each of the common bit line contacts, word lines between the first active source contacts and the common bit line contacts and between the common bit line contacts and the second active source contacts, bit lines on the common bit line contacts, variable resistance layers connected to the second active source contacts, the word lines, and the bit lines, spin-orbit torque (SOT) layers connected to the first active source contacts on the variable resistance layers, the word lines, and the bit lines, source line contacts on the SOT layers, and source lines connected to the source line contacts.

First claim

What is claimed is:

1. A variable resistance memory device comprising:
a plurality of active regions spaced apart from each other in a first direction and a second direction;
a plurality of first active source contacts on first ends of the plurality of active regions;
a plurality of second active source contacts on second ends of the plurality of active regions;
a plurality of bit lines extending in the second direction, the plurality of bit lines including at least a first bit line between a row of the plurality of first active source contacts and a row of the plurality of second active source contacts;
a plurality of common bit line contacts electrically connecting central portions or central edges of the plurality of active regions with the plurality of bit lines;
a plurality of word lines extending in the first direction, the plurality of word lines including at least a first word line between a column of the plurality of first active source contacts and a column of the plurality of common bit line contacts and at least a second word line between the column of the plurality of common bit line contacts and a column of the plurality of the second active source contacts;
a plurality of variable resistance layers over the plurality of active regions, the plurality of word lines, and the plurality of bit lines, the plurality of variable resistance layers electrically connected to the plurality of second active source contacts;
a plurality of spin-orbit torque (SOT) layers on the plurality of variable resistance layers and over the plurality of active regions, the plurality of word lines, and the plurality of bit lines, the plurality of SOT layers electrically connected to the plurality of first active source contacts;
a plurality of source lines extending in the second direction; and
a plurality of source line contacts electrically connecting the plurality of SOT layers and the plurality of source lines.

2. The variable resistance memory device of claim 1 , wherein
each of the plurality of variable resistance layer comprises a magnetic tunnel junction (MTJ) structure, and
the MTJ structure comprises an SOT-type MTJ structure.

3. The variable resistance memory device of claim 2 , wherein the MTJ structure comprises at least one of a perpendicular MTJ (PMTJ) or an in-plane MTJ (IMTJ).

4. The variable resistance memory device of claim 1 , wherein each of the plurality of active regions has an elliptical shape having a major axis and a minor axis.

5. The variable resistance memory device of claim 1 , wherein the plurality of active regions are inclined in a diagonal direction between the first direction and the second direction.

6. The variable resistance memory device of claim 1 , wherein the plurality of active regions are perpendicular to the first direction and parallel to the second direction.

7. The variable resistance memory device of claim 1 , wherein
the plurality of variable resistance layers comprises a plurality of magnetic tunnel junction (MTJ) structures over the plurality of active regions,
the plurality of SOT layers are on the plurality of MTJ structures, and
the plurality of MTJ structures comprise SOT-type MTJ structures.

8. The variable resistance memory device of claim 1 , further comprising:
first middle connection structures electrically connected to the plurality of SOT layers; and
first wiring structures between and electrically connecting the first middle connection structures and the plurality of first active source contacts such that electric paths between the plurality of first active source contacts and the plurality of SOT layers are shifted by the first wiring structures.

9. The variable resistance memory device of claim 1 , further comprising:
second middle connection structures electrically connected to the plurality of variable resistance layers; and
second wiring structures between and electrically connecting the second middle connection structures and the plurality of second active source contacts such that electrical paths between the plurality of second active source contacts and the plurality of variable resistance layers are shifted by the second wiring structures.

10. The variable resistance memory device of claim 1 , wherein the plurality of SOT layers protrude from one side surface of each of the variable resistance layers in a cross-sectional view.

11. A variable resistance memory device comprising:
a plurality of active regions spaced apart from each other in a first direction and a second direction;
a plurality of first active source contacts on first ends of the plurality of active regions;
a plurality of second active source contacts on second ends of the plurality of active regions;
a plurality of bit lines extending in the second direction, the plurality of bit lines including at least a first bit line between a row of the plurality of first active source contacts and a row of the plurality of second active source contacts;
a plurality of common bit line contacts electrically connecting central portions of the plurality of active regions with the plurality of bit lines;
a plurality of word lines extending in the first direction, the plurality of word lines including at least a first word line between a column of the plurality of first active source contacts and a column of the plurality of common bit line contacts and at least a second word line between the column of the plurality of common bit line contacts and a column of the plurality of second active source contacts;
a plurality of first middle connection contacts;
first wiring structures electrically connecting the plurality of first active source contacts and the plurality of first middle connection contacts such that electrical paths between the plurality of first active source contacts and the plurality of first middle connection contacts are shifted by the first wiring structures;
a plurality of second middle connection contacts;
second wiring structures electrically connecting the plurality of second active source contacts and the plurality of second middle connection contacts such that electrical paths between the plurality of second active source contacts and the plurality of second middle connection contacts are shifted by the second wiring structures;
a plurality of variable resistance layers over the plurality of active regions, the plurality of word lines, and the plurality of bit lines, the plurality of variable resistance layers having lower portions electrically connected to the plurality of second middle connection contacts;
a plurality of spin-orbit torque (SOT) layers on the plurality of variable resistance layers and over the plurality of active regions, the plurality of word lines, and the plurality of bit lines, the plurality of SOT layers having lower portions electrically connected to the plurality of first middle connection contacts;
a plurality of source lines extending in the second direction; and
a plurality of source line contacts electrically connecting the plurality of SOT layers and the plurality of source lines.

12. The variable resistance memory device of claim 11 , wherein, in a top view, the plurality of source line contacts are between the plurality of first middle connection contacts in the first direction.

13. The variable resistance memory device of claim 11 , wherein
one edge portion of each of the plurality of SOT layers is recessed from a corresponding edge portion of each of the plurality of first middle connection contacts in a cross-sectional view, and
another edge portion of each of the plurality of SOT layers is recessed from another corresponding edge of each of the pl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yong Jae
• Byun Jihun

Classifications

• H10N50/80

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title