Memory device, semiconductor device, and method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-11716859-B2
Application number	US-202117319115-A
Country	US
Kind code	B2
Filing date	May 13, 2021
Priority date	May 13, 2021
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate comprising a transistor, wherein the transistor has a source region and a drain region; and
an interconnect structure disposed over the semiconductor substrate, wherein the interconnect structure comprises:
a plurality of interlayer dielectric layers over the semiconductor substrate;
a first via embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor;
a memory cell disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via; and
a first signal line embedded in a first middle interlayer dielectric layer among the plurality of interlayer dielectric layers, wherein the first signal line extends on the semiconductor substrate along a first direction, and along a thickness direction perpendicular to the first direction, a vertical projection of the first signal line is spaced apart from a vertical projection of the memory cell.

2. The semiconductor device according to claim 1 , wherein the transistor has a gate structure disposed between the source region and the drain region and extending along a second direction perpendicular to the first direction and the thickness direction.

3. The semiconductor device according to claim 2 , wherein the interconnect structure further comprises:
a second via embedded in a bottommost interlayer dielectric layer among the plurality of interlayer dielectric layers, wherein
the first middle interlayer dielectric layer is located over the bottommost interlayer dielectric layer among the plurality of interlayer dielectric layers, wherein the second via and the first signal line are electrically connected with the source region of the transistor, the first signal line extends on the bottommost interlayer dielectric layer along the first direction.

4. The semiconductor device according to claim 3 , wherein the first via penetrates through the bottommost interlayer dielectric layer and the first middle interlayer dielectric layer.

5. The semiconductor device according to claim 3 , wherein the first via is located over the first middle interlayer dielectric layer.

6. The semiconductor device according to claim 5 , wherein the interconnect structure further comprises:
a third via embedded in the bottommost interlayer dielectric layer among the plurality of interlayer dielectric layers; and
a landing pad embedded in the first middle interlayer dielectric layer among the plurality of interlayer dielectric layers, wherein the third via and the landing pad are electrically connected with the drain region of the transistor, the landing pad extends on the bottommost interlayer dielectric layer along the first direction.

7. The semiconductor device according to claim 6 , wherein the first via is electrically connected with the landing pad.

8. The semiconductor device according to claim 3 , wherein the interconnect structure further comprises:
a second signal line embedded in a second middle interlayer dielectric layer among the plurality of interlayer dielectric layers, wherein the second middle interlayer dielectric layer is located over the first middle interlayer dielectric layer, the second middle interlayer dielectric layer is located within the at least two interlayer dielectric layers, the second signal line is electrically connected with the gate structure of the transistor, the second signal line extends over the first middle interlayer dielectric layer along the second direction.

9. The semiconductor device according to claim 8 , wherein the interconnect structure further comprises:
a third signal line embedded in a topmost interlayer dielectric layer among the plurality of interlayer dielectric layers, wherein the topmost interlayer dielectric layer is located over the at least two interlayer dielectric layers, the third signal line is electrically connected with the memory device, and the third signal line extends over the at least two interlayer dielectric layers along the first direction.

10. A memory device, comprising:
a first transistor and a second transistor;
a plurality of dielectric layers over the first transistor and the second transistor;
a first via extending through the plurality of dielectric layers along a first direction;
a second via extending through the plurality of dielectric layers along the first direction; and
a memory cell disposed over the plurality of dielectric layers, wherein the memory cell is electrically connected with a first drain region of the first transistor through the first via, and electrically connected with a second drain region of the second transistor through the second via.

11. The memory device according to claim 10 , wherein the first transistor has a first gate structure aside the first drain region, the second transistor has a second gate structure aside the second drain region, the first gate structure is substantially parallel with the second gate structure, and the first gate structure extends along a second direction perpendicular to the first direction.

12. The memory device according to claim 11 , further comprising:
a first source line and a second source line disposed between the first transistor and the memory cell, wherein the first source line and the second source line are arranged along the second direction, the first source line is substantially parallel with the second source line, the first source line extends along a third direction perpendicular to the first direction and intersected with the second direction, the first source line is electrically connected with a first source region of the first transistor, and the second source line is electrically connected with a second source region of the second transistor.

13. The memory device according to claim 12 , wherein the first source line and the second source line are disposed aside the first via and the second via, and are embedded in the plurality of dielectric layers.

14. The memory device according to claim 12 , wherein the first source line and the second source line are disposed under the plurality of dielectric layers.

15. The memory device according to claim 12 , further comprising:
a first rerouting word line and a second rerouting word line disposed aside the first via and the second via and between the first source line and the memory cell, wherein the first rerouting word line and the second rerouting word line arranged along the third direction, the first rerouting word line is substantially parallel with the second rerouting word line, the first rerouting word line extends along the second direction, the first rerouting word line is electrically connected with the first gate structure, and the second source line is electrically connected with the second gate structure.

16. The memory device according to claim 12 , further comprising:
a bit line disposed over the memory unit and overlapped with the memory cell, the first via and the second via, wherein the bit line extends along the third direction, the bit line is electrically connected with the memory cell.

17. The memory device according to claim 12 , further comprising:
at least one dummy transistor disposed between the first transistor and the second transistor, wherein the at least one dummy transistor has a dummy gate structure substantially parallel with the first gate structure and disposed between the first gate structure and the second gate struct

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Diaz Carlos H
• Lin Shy-Jay
• Song Ming-Yuan

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B61/20 Primary

  comprising components having three or more electrodes, e.g. transistors · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L23/5283

  Electricity · mapped topic